The V_CC pin is the current limited regulated output based supporting an accuracy of ±2.5%. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UV_SUP threshold, the regulator turns off until the input voltage returns above the UV_SUPR level. The device uses the voltage regulator during Init mode to determine which function the WKRQ/INH, and what the IO voltage is when the 5V LDO is used. The device monitors V_CC for under-voltage. The device control method and whether fail-safe mode is enabled determine the behavior of the of the device for these events. Fail-safe mode is always active when the device is in pin control. In SPI control, the state diagram shows two paths: fail-safe mode enabled and fail-safe mode disabled. The path followed depends on whether fail-safe mode is enabled or disabled in 8'h17[0] FSM_DIS.

For an under-voltage event, V_CC is less than or equal to UV_CCF. After the t_UVFLTR time, the device pulls nRST low and transition to restart mode, if fail-safe disabled, or fail-safe mode. When entering either mode the SWE timer, t_{INACT_FS} starts and for SPI control the mode counter increments and the appropriate interrupt flags are set. To exit fail-safe mode the under-voltage has to clear and a wake event takes place prior to the SWE timer timing out. If the under-voltage event has not cleared when the wake event takes place or if the SWE timer times out the device enters sleep mode. Figure 6-3 shows how a UV_CC event is handled.