SLLA541 December   2020 TCAN1144-Q1 , TCAN1146-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Component Failure Modes Effects and Diagnostics Analysis (FMEDA)
    1. 2.1 Random Fault Estimation
      1. 2.1.1 Fault Rate Estimation Theory for Packaging
      2. 2.1.2 Fault Estimation Theory for Silicon Permanent Faults
      3. 2.1.3 Fault Estimation Theory for Silicon Transient Faults
      4. 2.1.4 The Classification of Failure Categories and Calculation
    2. 2.2 Using the FMEDA Spreadsheet Tool
      1. 2.2.1 Mission Profile Tailoring Tab
        1. 2.2.1.1 Confidence Level
        2. 2.2.1.2 Geographical Location
        3. 2.2.1.3 Life Cycle
        4. 2.2.1.4 Use Case Thermal Management Control (Theta-Ja) and Use Case Power
        5. 2.2.1.5 Safe vs Non-Safe (Safe Fail Fraction) for Each Component Type
        6. 2.2.1.6 Analog FIT Distribution Method
        7. 2.2.1.7 Operational Profile
      2. 2.2.2 Pin Level Tailoring Tab
      3. 2.2.3 Function and Diag Tailoring Tab
      4. 2.2.4 Diagnostic Coverage Tab
      5. 2.2.5 Customer Defined Diagnostics Tab
      6. 2.2.6 Totals - ISO26262 Tab
      7. 2.2.7 Details - ISO26262 Tab
    3. 2.3 Example Calculation of Metrics
      1. 2.3.1 Assumptions of Use for Calculation of Safety Metrics
      2. 2.3.2 Summary of ISO 26262 Safety Metrics at Device Level

2.2.6 Totals - ISO26262 Tab

This tab is informational only. There are no selections the user can make in this tab.

The 'Totals - ISO26262' tab contains the results of the chip level FMEDA metrics based on the selections in the previous tabs. This tab summarizes the metrics as described by the ISO 26262 functional safety standard. The top table breaks out the overall FIT and diagnostic coverage for permanent faults of the die, transient faults of the die, package faults, and finally the overall sum of faults for each row. The following information is provided:

  • Total FIT (Raw FIT): The total base failure rate of the device using the described base FIT model under the environmental conditions input in the 'Mission Profile Tailoring' tab.
  • Safety related FIT: A subset of the total FIT that includes only the design blocks or device pins that are indicated as safety related on the 'Pin Level Tailoring' and 'Function and Diag Tailoring' tabs.
  • Probabilistic Metrics for random Hardware Failures (PMHF) (in FIT): The selection of diagnostics in the 'Pin Level Tailoring' and 'Function and Diag Tailoring' tabs directly impact this percentage.
  • Single Point Fault Metric - SPFM: The percentage coverage for detecting or preventing single point faults.
  • Latent Fault Metric - LFM: The percentage coverage for detecting or preventing latent faults.

There are also some intermediate calculations based on the terms in the ISO 26262 standard:

  • Total faults (λ)
  • Total safety related faults (λSR)
  • Total non safety related faults (λnSR)
  • Total safe faults (λS)
  • Total not safe faults (λnS).
  • Total faults with prob. of violate the SG (λPVSG)
  • Total single point faults (λSPF)
  • Total residual fualts (λRF)
  • Total multi point (primary) [non-PVSG] (λMPFPrimary)
  • Total multi point (secondary) [PVSG] (λMPFSecondary)
  • Total multi point detected faults (λMPF_det)
  • Total multi point latent faults (λMPF,l)

The concept of perceived faults is not applicable at the semiconductor level since the fault detection ability of the driver cannot be considered at this level of analysis.