SLLA565 September   2021 TUSB1044

 

  1.   Trademarks
  2. 1Introduction
  3. 2TUSB1044 Configuration and Control Implementation
    1. 2.1 TUSB1044 Four-Level Pins
      1. 2.1.1 I2C_EN
      2. 2.1.2 VIO_SEL
      3. 2.1.3 UEQ[1:0] and DEQ[1:0]
      4. 2.1.4 CFG[1:0]
    2. 2.2 TUSB1044 Two-Level Pins
      1. 2.2.1 FLIP, CTL0, and CTL1
      2. 2.2.2 DIR0 and DIR1
      3. 2.2.3 SWAP
      4. 2.2.4 HPDIN
      5. 2.2.5 SLP_S0#
  4. 3TUSB1044 I2C Mode Implementation
    1. 3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A
    2. 3.2 VOD Configuration, General_3 Register 0x0C
    3. 3.3 Upstream and Downstream Equalization Configuration Registers, UFP1_EQ, UFP2_EQ, DFP1_EQ, and DFP2_EQ Registers 0x10, 0x11, 0x20, 0x21
  5. 4Benefits of Using the I2C Mode Control
  6. 5TUSB1044 Host Implementation Example
  7. 6TPS6598X, TPS6599X Based I2C Control and Tuning
    1. 6.1 Enable PD Controller I2C Control of External Slaves
    2. 6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event
    3. 6.3 Example of I2C Configuration Upon Cable-Orientation Event and DP Configuration Event
    4. 6.4 Notes for Application
  8. 7References

4 Benefits of Using the I2C Mode Control

Upon implementation of I2C mode control of TUSB1044, especially for notebooks that have two USB Type-C ports supported by TPS65988 or TPS65994, expect to save 2 × 3 GPIOs of PD controller (pin 21 FLIP for cable orientation control, pin 22 CTL0 for USB3 select, and pin 23 CTL1 for DP mode select which make the PCB design easier with only I2C wires routed to the PD controller and HPD signal routed to the host platform.

Also, during the engineering phase of the project validation, there will always be tuning required to pass the USB and DP compliance test. I2C mode control allows the tuning to happen via a PD FW update which is available in the Operating System for most PD controllers so that engineers do not have to constantly change the resistor configuration and risk the damage to the PCB. Also, I2C mode allows engineers to separately tune the setting for individual lanes and also make USB and DP independent tuning available.

I2C mode allows less configuration resistor placement; therefore saving extra BOM cost and overall PCB space.

Table 4-1 shows the pin configuration comparison between the TUSB1044 in GPIO and I2C mode.

Table 4-1 Pin Configuration Comparison in GPIO and I2C Mode
Pin DefinitionGPIO ModeI2C Mode
CFG04-level inputNC
CFG14-level inputNC
FLIP/SCL2-level FLIP inputSCL
CTL0/SDA2-level CTL0 inputSDA
CTL12-level inputNC
DEQ14-level EQ inputNC
DEQ04-level EQ inputNC
UEQ0/A04-level EQ input4-level I2C address input
UEQ1/A14-level EQ input4-level I2C address input
DIR02-level inputNC
DIR12-level inputNC