SLLA565 September   2021 TUSB1044

 

  1.   Trademarks
  2. 1Introduction
  3. 2TUSB1044 Configuration and Control Implementation
    1. 2.1 TUSB1044 Four-Level Pins
      1. 2.1.1 I2C_EN
      2. 2.1.2 VIO_SEL
      3. 2.1.3 UEQ[1:0] and DEQ[1:0]
      4. 2.1.4 CFG[1:0]
    2. 2.2 TUSB1044 Two-Level Pins
      1. 2.2.1 FLIP, CTL0, and CTL1
      2. 2.2.2 DIR0 and DIR1
      3. 2.2.3 SWAP
      4. 2.2.4 HPDIN
      5. 2.2.5 SLP_S0#
  4. 3TUSB1044 I2C Mode Implementation
    1. 3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A
    2. 3.2 VOD Configuration, General_3 Register 0x0C
    3. 3.3 Upstream and Downstream Equalization Configuration Registers, UFP1_EQ, UFP2_EQ, DFP1_EQ, and DFP2_EQ Registers 0x10, 0x11, 0x20, 0x21
  5. 4Benefits of Using the I2C Mode Control
  6. 5TUSB1044 Host Implementation Example
  7. 6TPS6598X, TPS6599X Based I2C Control and Tuning
    1. 6.1 Enable PD Controller I2C Control of External Slaves
    2. 6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event
    3. 6.3 Example of I2C Configuration Upon Cable-Orientation Event and DP Configuration Event
    4. 6.4 Notes for Application
  8. 7References

3 TUSB1044 I2C Mode Implementation

When in the I2C mode, the TUSB1044 I2C address is defined by the UEQ0/A0 and UEQ1/A1 pin as shown in Table 3-1.

Table 3-1 TUSB1044 I2C Slave Address Configuration
Pin Combination TUSB1044 I2C Address
UEQ1/A1 Pin2 Level UEQ0/A0 Pin 35 Level 7-bit I2C Address Bit 0 (W/R)
0 0 0x44 0/1
0 R 0x45 0/1
0 F 0x46 0/1
0 1 0x47 0/1
R 0 0x20 0/1
R R 0x21 0/1
R F 0x22 0/1
R 1 0x23 0/1
F 0 0x10 0/1
F R 0x11 0/1
F F 0x12 0/1
F 1 0x13 0/1
1 0 0x0C 0/1
1 R 0x0D 0/1
1 F 0x0E 0/1
1 1 0x0F 0/1

Table 3-2 lists the memory-mapped registers for the TUSB1044. Consider all register offset addresses not listed in Table 3-2 as reserved locations and do not modify the reserved register contents.

Table 3-2 TUSB1044 Register Contents
Offset Acronym Register Name

Ah

General_1

General Register 1

Bh

General_2

General Register 2

Ch

General_3

General Register 3

10h

UFP2_EQ

UFP2 EQ Control

11h

UFP1_EQ

UFP1 EQ Control

12h

DisplayPort_1

AUX Snoop Status

13h

DisplayPort_2

DP Lane Enable and Disable Control

1Bh

SOFT_RESET

I2C and DPCS Soft Reset

20h

DFP2_EQ

DFP2 EQ Control

21h

DFP1_EQ

DFP1 EQ Control

22h

USB3_MISC

Misc USB3 Controls

23h

USB3_LOS

USB3 LOS Threshold Controls