SLLA565 September   2021 TUSB1044

 

  1.   Trademarks
  2. 1Introduction
  3. 2TUSB1044 Configuration and Control Implementation
    1. 2.1 TUSB1044 Four-Level Pins
      1. 2.1.1 I2C_EN
      2. 2.1.2 VIO_SEL
      3. 2.1.3 UEQ[1:0] and DEQ[1:0]
      4. 2.1.4 CFG[1:0]
    2. 2.2 TUSB1044 Two-Level Pins
      1. 2.2.1 FLIP, CTL0, and CTL1
      2. 2.2.2 DIR0 and DIR1
      3. 2.2.3 SWAP
      4. 2.2.4 HPDIN
      5. 2.2.5 SLP_S0#
  4. 3TUSB1044 I2C Mode Implementation
    1. 3.1 TUSB1044 Operating Mode Configuration, General_1 Register, 0x0A
    2. 3.2 VOD Configuration, General_3 Register 0x0C
    3. 3.3 Upstream and Downstream Equalization Configuration Registers, UFP1_EQ, UFP2_EQ, DFP1_EQ, and DFP2_EQ Registers 0x10, 0x11, 0x20, 0x21
  5. 4Benefits of Using the I2C Mode Control
  6. 5TUSB1044 Host Implementation Example
  7. 6TPS6598X, TPS6599X Based I2C Control and Tuning
    1. 6.1 Enable PD Controller I2C Control of External Slaves
    2. 6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event
    3. 6.3 Example of I2C Configuration Upon Cable-Orientation Event and DP Configuration Event
    4. 6.4 Notes for Application
  8. 7References

6.2 Example of I2C Configuration Upon PD Controller PoR Event and Detach Event

The PD controller allows different trigger events to initiate I2C behaviors. On POR, the control register (0x0A), and configuration registers (0x10, 0x11, 0x20, 0x21, part of 0x0C) can be initiated with a pre-defined value.

  • 0x0A, write to 0x10 to enable EQ override by I2C, and disable the channels
  • 0x0C, write to 0x4C, for example, to enable VOD, DCGain override by I2C, and also to configure the VOD setting to #3 defined in Table 2-4
  • 0x10, 0x11, can be configured to 0x77, for example, to set the UEQ to #7 of EQ setting as defined in Figure 2-1
  • 0x20, 0x21, could be configured to 0x33, for example, to set the DEQ to #3 of EQ setting defined in Figure 2-1
Note: The settings in the previous list are for reference and the most favorable setting is achieved from PCB design and tuning with SI test and compliance results. The formatted data is as shown in Table 6-1.
Table 6-1 Example of TUSB1044 Configuration Register Setting
Configuration Register Offset Data Trigger Event
0x10 0x7710 PoR, *Attach
0x11 0x7711 PoR, *Attach
0x20 0x3320 PoR, *Attach
0x21 0x3321 PoR, *Attach
0x0C 0x4C0C PoR, *Attach

Figure 6-1 is an example of defining I2C configuration to TUSB1044 over PD controller upon trigger events Power on Reset, where “0x10” is the config data for register offset “0x0A” with a total byte count to be ‘2’ defined in the Data Length.


GUID-20210707-CA0I-SKNZ-1RHR-T2M3P95P2SRX-low.png

Figure 6-1 Example of TUSB1044 Reset Upon PD Controller PoR

Upon detach event, reset the control register to the same value as PoR.