SLLA626 September   2023 HD3SS460

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Migrating from TI HD3SS460 to TMUXHS4446
    1. 2.1 Pinout Differences
    2. 2.2 Package Differences
    3. 2.3 Protocol Differences
  6. 3PCB Layout Recommendations
  7. 4Summary
  8. 5References

2.1 Pinout Differences

Table 2-1 includes the pin out differences between HD3SS460 QFN (RHR) (28) and HD3SS460 QFN (RHR) (30), and TMUXHS4446 QFN (RET) (40). TMUXHS4446 has additional unique pins due to the addition of the option to use I2C as the control interface, and these pins are described in Table 2-2.

Table 2-1 Pinout Differences
HD3SS460 TMUXHS4446 Description
Name Pin Name Pin
RHR RHN
VCC 22 23 VCC 4, 7, 10, 23, 26, 29, 32 Power
GND PAD 13, 28, PAD GND 15, 18, 37 Ground
POL 3 3 - - Provides MUX control
AMSEL 8 8 - - Provides MUX configurations
EN 17 18 - - Enable signal; also provides MUX control
CRX1p,n 1, 2 1, 2 CRX1p,n 25, 24 Connector-side, high speed differential ± signals for USB-C RX/TX pins
CTX1p,n 4, 5 4, 5 CTX1p,n 28, 27 Connector-side, high speed differential ± signals for USB-C TX/RX pins
CRX2p,n 6, 7 6, 7 CRX2p,n 34, 33 Connector-side, high speed differential ± signals for USB-C RX/TX pins
CTX2p,n 9, 10 9, 10 CTX2p,n 31, 30 Connector-side, high speed differential ± signals for USB-C TX/RX pins
LnAn,p 15, 16 16, 17

DP0n,p

 40, 39 System-side, high speed differential ± signals for DisplayPort DP0
LnBn,p 18, 19 19, 20 DP1n,p 3, 2 System-side, high speed differential ± signals for DisplayPort DP1
LnCn,p 20, 21 21, 22 DP2n,p 6, 5 System-side, high speed differential ± signals for DisplayPort DP2
LnDn,p 23, 24 24, 25 DP3n,p 9, 8 System-side, high speed differential ± signals for DisplayPort DP3
SSTXn,p 25, 26 26, 27 SSTXn,p 12, 11 System-side, high speed differential ± signals for USB TX/RX pins
SSRXn,p 27, 28 29, 30 SSRXn,p 17, 16 System-side, high speed differential ± signals for USB RX/TX pins
CSBU1,2 11, 12 11, 12 CSBU1,2 - Connector-side, low speed SBU signal for USB-C SBU pin
SBU1,2 13, 14 14, 15 SBU1,2 22, 21 Connector-side, low speed SBU signal for USB-C SBU pin
Table 2-2 TMUXHS4446 Additional Pins
TMUXHS4446 Description
Name Pin
AUXn,p 20, 19 System-side, low speed SBU signal for USB-C SBU pins
MODE0 1 Control mode selection
MODE0 = 1, I2C control
MODE0 = 0, GPIO or pin control through CONF[2:0]
MODE1 13

I2C logic level control (MODE0 = 1)
MODE1 = 0, 1.8V I2C logic level
MODE1 = 1, 3.3 V I2C logic level
CONF0

35

GPIO control (MODE0 = 0)
Switch configuration control for high-speed and low-speed pins. Refer to Device Functional Modes section for details.
A1 I2C control (MODE0 = 1)
Configurable I2C target address bit
CONF1 36 GPIO control (MODE0 = 0)
Switch configuration control for high-speed and low-speed pins. Refer to Device Functional Modes section for details.
SCL I2C control (MODE0 = 1)
I2C clock input
CONF2 38 GPIO control (MODE0 = 0)
Switch configuration control for high-speed and low-speed pins. Refer to Device Functional Modes section for details.
SDA

I2C control (MODE0 = 1)
I2C data input
A0 14 I2C control (MODE0 = 1)
Configurable I2C target address bit