SLLA628 September   2023 THVD1424

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Use Case Domain of RS-485
    1. 1.1 RS-485 Compliant Transmitter
    2. 1.2 RS-485 Compliant Receiver
    3. 1.3 RS-485 Transceiver Use Case Variability
  5. 2Traditional RS-485 Design Process
    1. 2.1 Design Process Overview
    2. 2.2 Requirement Definition
      1. 2.2.1 Bus Voltage and Logic Voltage (VCC and VIO):
      2. 2.2.2 Number of Communication Nodes Supported plus Static vs. Dynamic Systems
      3. 2.2.3 Max Bus Length, Network Topology, Emission Concerns, and Data Rate Required
      4. 2.2.4 Duplex
      5. 2.2.5 Protection Needs
      6. 2.2.6 Additional Features of RS-485 Bus
    3. 2.3 IC Selection, Application Design, and Validation/Qualification
  6. 3One Multi-System Design: Flexible RS-485 with the THVD1424
    1. 3.1 Flexible Multi-System Design
    2. 3.2 Simplification of RS-485 Design Process Using THVD1424
      1. 3.2.1 Bus Voltage and Logic Voltage Supplies (VCC and VIO)
      2. 3.2.2 Number of Communication Nodes Supported plus Dynamic or Static Systems
      3. 3.2.3 Max Bus Length, Network Topology, Data Rate, and Emissions Concerns
      4. 3.2.4 Duplex
      5. 3.2.5 Protection Needs
      6. 3.2.6 Additional Features
  7. 4Summary
  8. 5References

1.1 RS-485 Compliant Transmitter

A RS-485 compliant transmitter has a few key requirements to be compliant with the standard – while this is not an exhaustive list – these tend to be the most critical across applications. The first is the output differential voltage magnitude – which is typically denoted |VOD| - which requires the magnitude of the driver to be a minimum of 1.5 V across a 54 Ω load – which is intended to show that the transmitter can drive 32 Unit Loads in Parallel with two 120 Ω termination resistors. It needs to be able to withstand an input common mode range of -7 V to 12 V – but this range can be expanded. In case of bus contention, two transmitters communicating at the same time, or a direct short to a voltage supply from a differential bus pin, or a short between differential bus pins the driver must limit the current magnitude to 250mA – this is typically denoted IOS. Finally, a more variable requirement, that of maximum differential transition time - which states that the transition time can be no more than a third of the bit time of the incoming signal.