SLLA643 August   2024 MCF8315C , MCF8315C-Q1 , MCF8316C-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Pin Design Recommendations
    1. 2.1 VM
    2. 2.2 Charge Pump: CPH, CPL, CP
    3. 2.3 Buck Converter: FB_BK, SW_BK, GND_BK
    4. 2.4 AVDD
    5. 2.5 DVDD
    6. 2.6 PGND, AGND, DGND
    7. 2.7 Thermal Pad
  6. 3MCF831xC Buck Regulator Overview
    1. 3.1 Buck Regulator Mode of Operation
    2. 3.2 Buck Regulator Output Voltage
    3. 3.3 Buck Power Sequencing
    4. 3.4 Buck Inductor Selection
    5. 3.5 MCF831xC Operation Without Buck Regulator
  7. 4MCF831xC IO Pins Design Recommendations
    1. 4.1 SPEED Pin
    2. 4.2 BRAKE, DIR, DRVOFF pins
    3. 4.3 EXT_CLK, EXT_WD
    4. 4.4 ALARM
    5. 4.5 DACOUT1, DACOUT2
    6. 4.6 SDA, SCL
    7. 4.7 nFAULT and FG pin
  8. 5MCF831xC PCB Schematic and Layout Recommendations
    1. 5.1 Single Ground Plane
    2. 5.2 Single Ground with AVDD Shorted to FB_BK
    3. 5.3 Two Grounds
  9. 6Summary
  10. 7References

4.1 SPEED Pin

Figure 4-1 shows the IO structure of the SPEED pin. SPEED pin has dual capability and can function either as an analog input (SPEED_MODE = 00b) or as digital input (SPEED_MODE = 01b or 11b). The SPEED pin has an 1MΩ internal pull-down resistor for noise immunity – pull-down resistors can be added externally for additional noise immunity.

SPEED Pin IO Structure Figure 4-1 SPEED Pin IO Structure

In analog mode, the SPEED input is connected to one of the ADC channels to convert the reference input to DUTY_CMD. In digital mode, SPEED input passes through a digital buffer followed by a user configurable glitch filter (using SPEED_PIN_GLITCH_FILTER to remove glitches up to 1µs) before getting converted into DUTY_CMD.

Table 4-1 SPEED Pin Glitch Filter Setting vs Glitch Width
SPEED_PIN_GLITCH_FILTER Glitch Width (µs)
00b No glitch filter
01b 0.2
10b 0.5
11b 1

When used, SPEED pin (analog or digital) needs to be directly connected to the input source.

When unused, SPEED pin needs to be tied to AGND directly.