SLLS552G December   2002  – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Driver Electrical Characteristics
    6. 8.6  Receiver Electrical Characteristics
    7. 8.7  Driver Switching Characteristics
    8. 8.8  Receiver Switching Characteristics
    9. 8.9  Receiver Equalization Characteristics
    10. 8.10 Power Dissipation
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Test Mode Driver Disable
      2. 10.4.2 Equivalent Input and Output Schematic Diagrams
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Noise Considerations for Equalized Receivers
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

10.4.1 Test Mode Driver Disable

If the input signal to the D pin is such that:

  1. the signal has signaling rate above 4 Mbps (for the SN65HVD21 and SN65HVD24),
  2. the signal has signaling rate above 6 Mbps (for the SN65HVD20 and SN65HVD23),
  3. the signal has average amplitude from 1.2 V to 1.6 V (1.4 V ± 200 mV), or
  4. the average signal amplitude remains in this range for 100 µs or longer,
then the driver may activate a test-mode during which the driver outputs are temporarily disabled. This can cause loss of transmission of data during the period that the device is in the test-mode. The driver is re-enabled and resumes normal operation whenever the above conditions are not true. The device is not damaged by this test mode.

Although rare, there are combinations of specific voltage levels and input data patterns within the operating conditions of the SN65HVD2x family which may lead to a temporary state where the driver outputs are disabled for a period of time.

Observations:

  1. The conditions for inadvertently entering the test mode are dependent on the levels, duration, and duty cycle of the logic signal input to the D pin. Operating input levels are specified as greater than 2 V for a logic HIGH input, and less than 0.8 V for a logic LOW input. Therefore, a valid steady-state logic input does not cause the device to activate the test mode
  2. Only input signals with frequency content above 2 MHz (4 Mbps) have a possibility of activating the test mode. Therefore, this issue should not affect the normal operation of the SN65HVD22 (500 kbps).
  3. For operating signaling rates of 4 Mbps (or above), the conditions stated above must remain true over a period of: 4 Mbps ×100 µs = 400 bits. Therefore, a normal short message does not inadvertently activate the test model.
  4. One example of an input signal which may cause the test mode to activate is a clock signal with frequency 3 MHz and 50% duty cycle (symmetric HIGH and LOW half-cycles) with logic HIGH levels of 2.4 V and logic LOW levels of 0.4 V. This signal applied to the D pin as a driver input would meet the criteria listed above, and may cause the test-mode to activate, which would disable the driver. This example situation may occur if the clock signal is generated from a microcontroller or logic chip with a 2.7-V supply.