SLLS902A
February 2010 – March 2024
SN65MLVD040
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Reccommended Operationg Conditions
5.3
Thermal Characteristics
5.4
Package Dissipation Ratings
5.5
Device Electrical Characteristics
5.6
Driver Electrical Characteristics
5.7
Reciver Electrical Charecteristics
5.8
Bus Input and Output Electrical Characteristics
5.9
Driver Switching Characterisitics
5.10
Reciever Switching Charecteristics
5.11
Typical Characteristics
6
Paramater Measurement Information
6.1
Equivalent Input and Output Schematic Diagrams
7
Application and Implementation
7.1
Application Information
7.1.1
Source Synchronous System Clock (SSSC)
7.1.1.1
Live Insertion/Glitch-Free Power Up/Down
8
Device and Documentation Support
8.1
Documentation Support
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
1
Features
Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates
(1)
Up to 250Mbps; Clock Frequencies Up to
125MHz
Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for Improved Signal Quality
–1V to 3.4V Common-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise
Bus Pins High Impedance When Driver Disabled or V
CC
≤ 1.5V
Independent Enables for each Driver and Receiver
Enhanced ESD Protection: 7kV HBM on all Pins
48 pin 7 X 7 QFN (RGZ)
M-LVDS Bus Power Up/Down Glitch Free