SLLS902A February   2010  – March 2024 SN65MLVD040

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Reccommended Operationg Conditions
    3. 5.3  Thermal Characteristics
    4. 5.4  Package Dissipation Ratings
    5. 5.5  Device Electrical Characteristics
    6. 5.6  Driver Electrical Characteristics
    7. 5.7  Reciver Electrical Charecteristics
    8. 5.8  Bus Input and Output Electrical Characteristics
    9. 5.9  Driver Switching Characterisitics
    10. 5.10 Reciever Switching Charecteristics
    11. 5.11 Typical Characteristics
  7. 6 Paramater Measurement Information
    1. 6.1 Equivalent Input and Output Schematic Diagrams
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Source Synchronous System Clock (SSSC)
        1. 7.1.1.1 Live Insertion/Glitch-Free Power Up/Down
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Package Dissipation Ratings

PACKAGEPCB JEDEC
STANDARD		TA ≤ 25°C
POWER RATING		DERATING FACTOR(1)
ABOVE TA = 25°C		TA = 85°C
POWER RATING
RGZLow-K(2)1298 mW12.98 mW/°C519 mW
RGZHigh-K(3)3448 mW34.48 mW/°C1379 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.