• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TUSB1210 Stand-Alone USB Transceiver Chip Silicon

    • SLLSE09J November   2009  – July 2021 TUSB1210

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • TUSB1210 Stand-Alone USB Transceiver Chip Silicon
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 OTG ID Electrical
    12. 6.12 Power Characteristics
    13. 6.13 Switching Characteristics
    14. 6.14 Timing Requirements
      1. 6.14.1 Timing Parameter Definitions
      2. 6.14.2 Interface Target Frequencies
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
    2. 10.2 Layout Guidelines
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TUSB1210 Stand-Alone USB Transceiver Chip Silicon

1 Features

  • USB2.0 PHY transceiver chip, designed to interface with a USB controller through a ULPI interface, fully compliant with:
    • Universal serial bus specification Rev. 2.0
    • On-the-go supplement to the USB 2.0 specification Rev. 1.3
    • UTMI+ low pin interface (ULPI) specification Rev. 1.1
    • ULPI 12-pin SDR interface
  • DP/DM line external component compensation (patent #US7965100 B1)
  • Interfaces to host, peripheral and OTG device cores; optimized for portable devices or system ASICs with built-in USB OTG device core
  • Complete USB OTG physical front-end that supports host negotiation protocol (HNP) and session request protocol (SRP)
  • VBUS overvoltage protection circuitry protects VBUS pin in range –2 V to 20 V
  • Internal 5-V short-circuit protection of DP, DM, and ID pins for cable shorting to VBUS pin
  • ULPI interface:
    • I/O interface (1.8 V) optimized for nonterminated 50 Ω line impedance
    • ULPI CLOCK pin (60 MHz) supports input and output clock configurations
    • Fully programmable ULPI-compliant register set
  • Full industrial grade operating temperature range from –40°C to 85°C
  • Available in a 32-pin quad flat no lead [QFN (RHB)] package

2 Applications

  • Mobile phones
  • Portable computers
  • Tablet devices
  • Video game consoles
  • Desktop computers
  • Portable music players

3 Description

The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI interface. The device supports all USB2.0 data rates (high-speed 480 Mbps, full-speed 12 Mbps, and low-speed 1.5 Mbps), and is compliant to both host and peripheral modes. The device additionally supports a UART mode and legacy ULPI serial modes. TUSB1210 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including HNP and SRP.

The DP/DM external component compensation in the transmitter compensates for variations in the series impendence in order to match with the data line impedance and the receiver input impedance, to limit data reflections and thereby improve eye diagrams.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TUSB1210 VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.
GUID-C92BC245-EF9B-4AA9-9A6C-C920E43DAEA3-low.gif Diagram

4 Revision History

Changes from Revision I (December 2019) to Revision J (July 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed the tDC, tDD OUTPUT CLOCK delay value From: MAX = 9 ns To: MAX = 5 ns in the Timing Requirements Go
  • Changed the tDC, tDD OUTPUT CLOCK delay value From: MIN = blank To: MIN = 1.2 ns in the Timing Requirements Go
  • Added the Related Documentation sectionGo

Changes from Revision H (June 2015) to Revision I (December 2019)

  • Changed the document from a data manual format to a TI data sheet format Go
  • Changed RHB Package 32-Pin OFN To: RHB Package 32-Pin VQFN in Pin Configuration and Functions Go
  • Changed the HBM value From: ±2 V To : ±2000 V in the ESD Ratings Go
  • Changed the tSC, tSD INPUT CLOCK value From: MAX = 3 ns To: MIN = 3 ns in the Timing Requirements Go
  • Changed the tSC, tSD OUTPUT CLOCK value From: MAX = 6 ns To: MIN = 6 ns in the Timing Requirements Go
  • Deleted section Via Channel from the Mechanical Packaging and Orderable Information section Go

Changes from Revision G (October 2014) to Revision H (June 2015)

  • Move Storage Temperature From: ESD Ratings To: Absolute Maximum Ratings Go
  • Changed the Handling Ratings table To: ESD Ratings Go

Changes from Revision F (July 2013) to Revision G (October 2014)

  • Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale