SLLSE09J November   2009  – July 2021 TUSB1210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 OTG ID Electrical
    12. 6.12 Power Characteristics
    13. 6.13 Switching Characteristics
    14. 6.14 Timing Requirements
      1. 6.14.1 Timing Parameter Definitions
      2. 6.14.2 Interface Target Frequencies
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. 7.5.1  VENDOR_ID_LO
      2. 7.5.2  VENDOR_ID_HI
      3. 7.5.3  PRODUCT_ID_LO
      4. 7.5.4  PRODUCT_ID_HI
      5. 7.5.5  FUNC_CTRL
      6. 7.5.6  FUNC_CTRL_SET
      7. 7.5.7  FUNC_CTRL_CLR
      8. 7.5.8  IFC_CTRL
      9. 7.5.9  IFC_CTRL_SET
      10. 7.5.10 IFC_CTRL_CLR
      11. 7.5.11 OTG_CTRL
      12. 7.5.12 OTG_CTRL_SET
      13. 7.5.13 OTG_CTRL_CLR
      14. 7.5.14 USB_INT_EN_RISE
      15. 7.5.15 USB_INT_EN_RISE_SET
      16. 7.5.16 USB_INT_EN_RISE_CLR
      17. 7.5.17 USB_INT_EN_FALL
      18. 7.5.18 USB_INT_EN_FALL_SET
      19. 7.5.19 USB_INT_EN_FALL_CLR
      20. 7.5.20 USB_INT_STS
      21. 7.5.21 USB_INT_LATCH
      22. 7.5.22 DEBUG
      23. 7.5.23 SCRATCH_REG
      24. 7.5.24 SCRATCH_REG_SET
      25. 7.5.25 SCRATCH_REG_CLR
      26. 7.5.26 VENDOR_SPECIFIC1
      27. 7.5.27 VENDOR_SPECIFIC1_SET
      28. 7.5.28 VENDOR_SPECIFIC1_CLR
      29. 7.5.29 VENDOR_SPECIFIC2
      30. 7.5.30 VENDOR_SPECIFIC2_SET
      31. 7.5.31 VENDOR_SPECIFIC2_CLR
      32. 7.5.32 VENDOR_SPECIFIC1_STS
      33. 7.5.33 VENDOR_SPECIFIC1_LATCH
      34. 7.5.34 VENDOR_SPECIFIC3
      35. 7.5.35 VENDOR_SPECIFIC3_SET
      36. 7.5.36 VENDOR_SPECIFIC3_CLR
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. 9 Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
    2. 10.2 Layout Guidelines
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RHB PackageTop View
Table 5-1 Pin Functions
PIN A/D TYPE LEVEL DESCRIPTION
NAME NO.
CFG 14 D I VDDIO REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz when 0, or 26 MHz when 1.
CLOCK 26 D O VDDIO ULPI 60 MHz clock on which ULPI data is synchronized.

Two modes are possible:

Input Mode: CLOCK defaults as an input.

Output Mode: When an input clock is detected on REFCLK pin (after 4 rising edges) then CLOCK will change to an output.
CPEN 17 D O VDD33 CMOS active-high digital output control of external 5 V VBUS supply
CS 11 D I VDDIO Active-high chip select pin. When low the IC is in power down and ULPI bus is tri-stated. When high normal operation. Tie to VDDIO if unused.
DATA0 3 D I/O VDDIO ULPI DATA input or output signal 0 synchronized to CLOCK
DATA1 4 D I/O VDDIO ULPI DATA input or output signal 1 synchronized to CLOCK
DATA2 5 D I/O VDDIO ULPI DATA input or output signal 2 synchronized to CLOCK
DATA3 6 D I/O VDDIO ULPI DATA input or output signal 3 synchronized to CLOCK
DATA4 7 D I/O VDDIO ULPI DATA input or output signal 4 synchronized to CLOCK
DATA5 9 D I/O VDDIO ULPI DATA input or output signal 5 synchronized to CLOCK
DATA6 10 D I/O VDDIO ULPI DATA input or output signal 6 synchronized to CLOCK
DATA7 13 D I/O VDDIO ULPI DATA input or output signal 7 synchronized to CLOCK
DIR 31 D O VDDIO ULPI DIR output signal
DM 19 A I/O VDD33 DM pin of the USB connector
DP 18 A I/O VDD33 DP pin of the USB connector
ID 23 A I/O VDD33 Identification (ID) pin of the USB connector
N/C 8, 15,16, 24, 25 — — — No connection
NXT 2 D O VDDIO ULPI NXT output signal
REFCLK 1 A I 3.3 V VDD33 Reference clock input (square-wave only). Tie to GND when pin 26 (CLOCK) is required to be Input mode. Connect to square-wave reference clock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is required to be Output mode. See pin 14 (CFG) description for REFCLK input frequency settings.
RESETB 27 D I VDDIO When low, all digital logic (except 32 kHz logic required for power up sequencing) including registers are reset to their default values, and ULPI bus is tri-stated. When high, normal USB operation.
STP 29 D I VDDIO ULPI STP input signal
VBAT 21 A power VBAT Input supply voltage or battery source
VBUS 22 A power VBUS VBUS pin of the USB connector
VDD15 12 A power 1.5 V internal LDO output. Connect to external filtering capacitor.
VDD18 28, 30 A power VDD18 External 1.8 V supply input. Connect to external filtering capacitor.
VDD33 20 A power VDD33 3.3 V internal LDO output. Connect to external filtering capacitor.
VDDIO 32 A I VDDIO External 1.8 V supply input for digital I/Os. Connect to external filtering capacitor.
GND Thermal Pad A power — Reference Ground