SLLSE11H March   2012  – March 2019 SN65HVD72 , SN65HVD75 , SN65HVD78

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation
    7. 7.7  Switching Characteristics: 250 kbps Device (SN65HVD72) Bit Time ≥ 4 µs
    8. 7.8  Switching Characteristics: 20 Mbps Device (SN65HVD75) Bit Time ≥50 ns
    9. 7.9  Switching Characteristics: 50 Mbps Device (SN65HVD78) Bit Time ≥20 ns
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Transient Protection
        2. 10.2.2.2 Isolated Bus Node Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

10.2.1.4 Receiver Failsafe

The differential receiver is failsafe to invalid bus states caused by:

  • Open bus conditions such as a disconnected connector
  • Shorted bus conditions such as cable damage shorting the twisted-pair together, or
  • Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a high when the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–). As shown in Electrical Characteristics, differential signals more negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always cause a high receiver output.

When the differential input signal is close to zero, it is still above the maximum VIT+ threshold of –20 mV, and the receiver output will be high. Only when the differential input is more than VHYS below VIT+ will the receiver output transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value, VHYS, as well as the value of VIT+.

SN65HVD72 SN65HVD75 SN65HVD78 noise_app_llse11.gifFigure 22. SN65HVD7x Noise Immunity