SLLSEJ2G July   2015  – March 2020 SN65DP159 , SN75DP159

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DP159 Mother Board Application Structure
      2.      DP159 Dongle Application Structure
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7.10 HDMI and DVI Main Link Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REDRIVER MODE
DR Data rate (Automatic Mode) 250 1000 Mbps
DR Data rate (full redriver mode) 250 6000 Mbps
tPLH Propagation delay time (low to high) 250 600 ps
tPHL Propagation delay time (high to low) 250 800 ps
tT1 Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps 45 ps
tT2 SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps 65
tT3 SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK 150MHz 100
tSK1(T) Intra-pair output skew SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; 40 ps
tSK2(T) Inter-pair output skew SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; 100 ps
tJITD1(1.4b) Total output data jitter DR = 2.97 Gbps, HDMI_SEL/A1 = NC, EQ_SEL/A0 = NC; PRE_SEL = NC; SLEW_CTL = H OE = H.
See Figure 10 at TTP3		 0.2 Tbit
tJITD1(2.0) Total output data jitter 3.4Gbps < Rbit ≤ 3.712Gps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.4 Tbit
3.712Gbps < Rbit < 5.94Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H -0.0332Rbit2 +0.2312 Rbit + 0.1998 Tbit
5.94Gbps ≤ Rbit ≤ 6.0Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H 0.8 Tbit
tJITC1(1.4b) Total output clock jitter CLK = 297 MHz 0.25 Tbit
tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit
RETIMER MODE
dR Data rate (Full retimer mode) 0.25 6 Gbps
dR Data rate (Automatic mode) 1.0 6 Gbps
dXVR Automatic redriver to retimer crossover Measured with input signal applied from 0 to 200 mVpp .75 1.0 1.25 Gbps
fCROSSOVER Crossover frequency hysteresis 250 MHz
PLLBW Data retimer PLL bandwidth Default loop bandwidth setting .4 1 MHz
tACQ Input clock frequency detection and retimer acquisition time 180 μs
IJT1 Input clock jitter tolerance Tested when data rate > 1.0 Gbps 0.3 Tbit
tT1 Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps 45 ps
tT2 SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps 65
tT3 SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK = 150 MHz 100
tDCD OUT_CLK ± duty cycle 40% 50% 60%
tSK_INTER Inter-pair output skew Default setting for internal inter-pair skew adjust, HDMI_SEL/A1 = NC 0.2 Tch
tSK_INTRA 0.15 Tbit
tJITC1(1.4b) Total output clock jitter CLK = 297 MHz 0.25 Tbit
tJITC1(2.0) Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit
tJITD2 Total output data jitter 3.4 Gbps < Rbit ≤ 3.712 Gbps 0.4 Tbit
3.712 Gbps < Rbit < 5.94 Gbps See (1)
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps 0.6
VOD_range Total TMDS data lanes output differential voltage 3.4 Gbps < Rbit ≤ 3.712 Gbps 335 mV
3.712 Gbps < Rbit < 5.94 Gbps See (2)
5.94 Gbps ≤ Rbit ≤ 6.0 Gbps 150
(1) –0.0332Rbit2 + 0.2312 Rbit + 0.1998
(2) –19.66 × (Rbit2) + (106.74 × Rbit) + 209.58