SLLSEJ2G July 2015 – March 2020 SN65DP159 , SN75DP159
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
GENERAL PARAMETERS | ||||||
VCC | Supply voltage | 3 | 3.3 | 3.6 | V | |
VDD | 1.00 | 1.1 | 1.27 | |||
TCASE | Case temperature for RSB package | 93.5 | °C | |||
TCASE | Case temperature for RGZ package | 92.7 | °C | |||
TA | Operating free-air temperature | SN75DP159 | 0 | 85 | °C | |
SN65DP159 | –40 | 85 | ||||
MAIN LINK DIFFERENTIAL PINS | ||||||
VID_PP | Peak-to-peak input differential voltage | 75 | 1200 | mv | ||
VIC | Input common mode voltage | 0 | 2 | V | ||
CAC | AC coupling capacitance | 75 | 100 | 200 | nF | |
dR | Data rate | 0.25 | 5 | Gbps | ||
VSADJ | TMDS-compliant swing voltage bias resistor (3) | 4.5 | 7.06 | 7.5 | kΩ | |
CONTROL PINS | ||||||
VI-DC | DC input voltage | Control pins | –0.3 | 3.6 | V | |
VIL(1) | Low-level input voltage at OE | 0.8 | V | |||
Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL | 0.3 | |||||
VIM(1) | No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL | 1 | 1.2 | 1.4 | V | |
VIH (1) | High-level input voltage at SLEW_CTL, OE(2) , PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL | 2.6 | V | |||
VOL | Low-level output voltage | 0.4 | V | |||
VOH | High-level output voltage | 2.4 | V | |||
IIH | High-level input current | –30 | 30 | µA | ||
IIL | Low-level input current | –10 | 10 | µA | ||
IOS | Short circuit output current | –50 | 50 | mA | ||
IOZ | High impedance output current | 10 | µA | |||
ROEPU | Pullup resistance on OE pin | 150 | 250 | kΩ |