11.1 Layout Guidelines

TI recommends to use at a minimum a four layer stack up to accomplish a low-EMI PCB design. TI recommends six layers because the SNx5DP149 is a two voltage rail device.

• Routing the high-speed input DisplayPort traces and TMDS output traces on the top layer avoids the use of vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the repeater inputs and from the repeater output to the subsequent receiver circuit. It is important to match the electrical length of these high speed traces to minimize both inter-pair and intra-pair skew.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high- frequency bypass capacitance significantly.
• The control pin pullup and pulldown resistors are shown in application section for reference. If a high is needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not use either resistors and leave the pin floating/No connect.

11.2 Layout Example

11.3 Thermal Considerations

On a high-K board: TI recommends to solder the PowerPAD™ onto the thermal land. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the SNx5DP149 device can operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.

On a low-K board: For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace connecting the GND pins to the thermal land must be used. A simulation shows R_θJA = 100.84°C/W allowing 545-mW power dissipation at 70°C ambient temperature.

A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package, SLMA002.