SLLSEN7E October   2015  – September 2017 TMDS171

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working (Retimer Mode Only)
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
      4. 8.4.4 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1  Local I2C Overview
        1. 8.5.1.1 BIT Access Tag Conventions
      2. 8.5.2  CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)
      3. 8.5.3  CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)
      4. 8.5.4  CSR BIT Field Definitions - Misc Control (offset: 00001001) (reset: 02h)
      5. 8.5.5  CSR BIT Field Definitions - Misc Control (offset: 00001010) (reset: B1h)
      6. 8.5.6  CSR BIT Field Definitions - Misc Control (offset: 00001011) (reset: 00h)
      7. 8.5.7  CSR BIT Field Definitions - Misc Control (offset: 00001100) (reset: 00h)
      8. 8.5.8  CSR BIT Field Definitions - Equalization Control Register (offset: 00001101) (reset: 01h)
      9. 8.5.9  CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)
      10. 8.5.10 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)
      11. 8.5.11 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)
      12. 8.5.12 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)
      13. 8.5.13 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)
      14. 8.5.14 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)
      15. 8.5.15 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)
      16. 8.5.16 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)
      17. 8.5.17 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)
      18. 8.5.18 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)
      19. 8.5.19 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)
      20. 8.5.20 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)
      21. 8.5.21 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)
      22. 8.5.22 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)
      23. 8.5.23 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)
      24. 8.5.24 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)
      25. 8.5.25 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)
      26. 8.5.26 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)
      27. 8.5.27 CSR BIT Field Definitions - RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Chain Showing DDC Connections
      2. 9.1.2 DDC Pull Up Resistors
    2. 9.2 Source Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Sink Side Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Parameter Measurement Information

TMDS171 TMDS171I Main_Link_Test_Circuit_sllsen7.gif Figure 4. TMDS Main Link Test Circuit
TMDS171 TMDS171I Input_Output_Timing_Measurements_sllsen7.gif Figure 5. Input/Output Timing Measurements
TMDS171 TMDS171I Output_Skew_Measurements_sllsen7.gif Figure 6. TMDS Output Skew Measurements
TMDS171 TMDS171I Output_Com_Mode_Measurement_sllsen7.gif Figure 7. HDMI/DVI TMDS Output Common Mode Measurement
TMDS171 TMDS171I pre-emphasis_differential_waveform_sllsen7.gif Figure 8. Output Differential Waveform
TMDS171 TMDS171I PRE_SEL_L_sllsen7.gif Figure 9. Output De-emphasis Waveform
TMDS171 TMDS171I pre_emphasis_circuit_sllsen7.gif
1. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, connector and another 1-8” of FR4. Trace width – 4 mils. 100 Ω differential impedance.
2. All Jitter is measured at a BER of 10-9
3. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1
4. AVCC = 3.3 V
5. RT = 50 Ω
6. The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.
Figure 10. Jitter Measurement Circuit
TMDS171 TMDS171I HDMI_Output_Jitter_Measurement_sllsen7.gif Figure 11. HDMI Output Jitter Measurement
TMDS171 TMDS171I HPD_Test_Circuit_sllsen7.gif Figure 12. HPD Test Circuit
TMDS171 TMDS171I HPD_Timing_Diagram1_sllsen7.gif Figure 13. HPD Timing Diagram No. 1
TMDS171 TMDS171I HPD_Logic_Disconnect_Timeout_sllsen7.gif Figure 14. HPD Logic Disconnect Timeout
TMDS171 TMDS171I Start_Stop_Condition_Timing_sllsen7.gif Figure 15. Start and Stop Condition Timing
TMDS171 TMDS171I SCL_SDA_Timing_sllsen7.gif Figure 16. SCL and SDA Timing
TMDS171 TMDS171I Propagation_Delay_Source_to_Sink_sllsen7.gif Figure 17. DDC Propagation Delay – Source to Sink
TMDS171 TMDS171I Propagation_Delay_Sink_to_Source_sllsen7.gif Figure 18. DDC Propagation Delay – Sink to Source
TMDS171 TMDS171I ARC_output_sllsen7.gif Figure 19. ARC Output
TMDS171 TMDS171I Rise_Fall_time_ARC_sllsen7.gif Figure 20. Rise/Fall Time of ARC