SLLSEO0D May   2015  – October 2017 TUSB211

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
      1. 7.3.1 Low Speed (LS) Mode
      2. 7.3.2 Full Speed (FS) Mode
      3. 7.3.3 High Speed (HS) Mode
      4. 7.3.4 Disable Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 For a Host Side Application
        2. 8.2.2.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Layout

Layout Guidelines

There is no need to break the USB signal trace. Thus, even with the TUSB211 powered down, or not populated, the USB link is still fully operational. To avoid the need for signal vias, routing the High Speed traces directly underneath the TUSB211 package, as illustrated in the PCB land pattern shown in Figure 8, is recommended.

Although the land pattern shown below has matched trace width to pad width, optimal impedance control is based on the user's own PCB stack-up. It is recommended to maintain 90 Ω differential routing underneath the device.

All dimensions are in millimetres (mm).

Layout Example

TUSB211 TUSB211I layout_sllseo9.gif Figure 8. DP and DM Routing Underneath Device Package