SLLSEO0D May   2015  – October 2017 TUSB211

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
      1. 7.3.1 Low Speed (LS) Mode
      2. 7.3.2 Full Speed (FS) Mode
      3. 7.3.3 High Speed (HS) Mode
      4. 7.3.4 Disable Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 For a Host Side Application
        2. 8.2.2.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RWB Package
12 Pin (X2QFN)
Top View
TUSB211 TUSB211I po_sllso9.gif

Pin Functions

PIN I/O INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO.
VCC 12 P N/A 3.3-V power
VREG 11 O RSTN asserted: 30 kΩ PD 1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF external capacitor to GND to stabilize the core.
FS, LS mode: 30 kΩ PD
HS mode: N/A
GND 10 P N/A Ground
RSTN 5 I 500 kΩ PU Device disable/enable.
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not driven.
EQ 6 I N/A USB High Speed boost select via external pull down resistor.
Sampled upon power up.
Auto selects min EQ when left floating.
Does not recognize real time adjustments.
D1P 2 I/O N/A USB High Speed positive port.
Orientation independent – Can face either upstream or downstream.
D1M 1 I/O N/A USB High Speed negative port.
Orientation independent – Can face either upstream or downstream.
D2P 7 I/O N/A USB High Speed positive port.
Orientation independent – Can face either upstream or downstream.
D2M 8 I/O N/A USB High Speed negative port.
Orientation independent – Can face either upstream or downstream.
TEST 3 I RSTN asserted: 500 kΩ PD No function. Leave floating.
ENA_HS 9 O RSTN asserted: 500kΩ PD Flag indicating that channel is in High Speed mode. Asserted upon:
  1. Detection of USB-IF High Speed test fixture from an unconnected state followed by transmission of USB TEST_PACKET pattern.
  2. Squelch detection following USB reset with a successful HS handshake [HS handshake is declared to be successful after single chirp J chirp K pair where each chirp is within 18 µs – 128 µs]

De-asserted upon detection of disconnect or suspend.
Can be left floating if not needed.
CD 4 O RSTN asserted: 500 kΩ PD Flag indicating that a USB device is attached.
Asserted from an unconnected state upon detection of DP or DM pull-up resistor.
De-asserted upon detection of disconnect.
Can be left floating if not needed.