SLLSES1D December 2015 – September 2020 HD3SS3220
PRODUCTION DATA
For this design example, use the parameters shown in Table 8-2.
PARAMETER | EXAMPLE | COMMENTS |
---|---|---|
VDD5 | 5.25 V | VDD5 is used to provide VCONN power to CC pins. Value of this supply should be ≥ 5 V to keep VCONN ≥ 4.75 V. |
System_VBUS | 5.25 V | VDD5 and System_VBUS can be shorted together; however careful consideration is needed to maintain desired VBUS and VCONN for the Type-C port. |
I2C I/O Supply | 3.3 V | 1.8 V is also an option. When using the 3.3-V supply, the customer must ensure that the VDD5 is 3 V and above. Otherwise the I2C may back power the device |
VCC33 | 3.3 V | 3-3.6 V range allowed. |
AC Coupling Capacitors for SS signals | 100 nF | 75-200 nF range allowed. For TX pairs only, RX pairs will be biased by host Receiver. Note that HD3SS3220 requires a common mode biasing of 0-2 V. If host receiver has bias voltage outside this range, appropriate additional ac coupling caps and biasing of HD3SS3220 RX pairs needed. |
Pull-up Resistors: DIR, ID, INT_N, VCONN_FAULT_N | 200 K | Smaller values can be used, but leakage needs to be considered for device power budget calculations. |
Pull-up Resistors: I2C | 4.7 K | |
Pull-up Resistors: CURRENT_MODE | 10 K | Example here is for 3 A. If 1.5 A or 900 mA needed different values are required. |
Decoupling Capacitors: VCONN Bulk | 100 μF | |
Decoupling Capacitors: VBUS Bulk | 150 μF |