SLLSET5A March   2016  – September 2016 ISO7821LLS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  DC Electrical Characteristics
    10. 6.10 DC Supply Current Characteristics
    11. 6.11 Timing Requirements for Distortion Correction Scheme
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Distortion-Correction Scheme
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8 Detailed Description

8.1 Overview

The ISO7821LLS device is an isolated LVDS buffer. The differential signal received on the LVDS input pins is first converted to CMOS logic levels. It is then transmitted across a silicon dioxide based capacitive isolation barrier using an On-Off Keying (OOK) modulation scheme. A high frequency carrier transmitted across the barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS outputs by a differential driver. This device incorporates advanced circuit techniques to maximize CMTI performance and minimize radiated emissions.

The ISO7821LLS device implements an eye-diagram improvement scheme to correct for signal distortions that are introduced in the LVDS receiver as well as the isolation channel. This enables the device to guarantee an eye closure of less than 30% at 125 Mbps, and less than 40% at 150 Mbps. The distortion correction scheme is optimized for operation with DC balanced data (for example 8b10b or equivalent) with a maximum run length of 6. The minimum data-rate of operation is also constrained to 50 Mbps. For general purpose data communication from 0 to 100 Mbps, the ISO782xLL family of devices should be considered.

The ISO7821LLS device is TIA/EIA-644-A standard compliant. The LVDS transmitter drives a minimum differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receiver is capable of detecting differential signal ≥50 mV in magnitude. The device consumes 11 mA per channel at 150 Mbps with 5-V supplies.

The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO7821LLS device.

8.2 Functional Block Diagram

ISO7821LLS fbd_sllset5.gif

8.3 Feature Description

The ISO7821LLS device is available in a two-channel configuration with a default differential-high output state. Table 1 lists the device features.

Table 1. Device Features

PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT DIFFERENTIAL OUTPUT
ISO7821LLS 1 Forward, 1 Reverse 5700 VRMS / 8000 VPK (1) 150 Mbps High
(1) See the Safety-Related Certifications section for detailed isolation ratings.

8.3.1 Distortion-Correction Scheme

The ISO7821LLS device implements a distortion-correction scheme to correct for signal distortions that are introduced in the LVDS receiver as well as the isolation channel. This scheme is optimized for a DC-balanced data-stream with a maximum run length of 6. One example of such a data stream is 8b10b encoded data. The minimum data rate supported by the ISO7821LLS device is 50 Mbps and the maximum is 150 Mbps.

Figure 25 shows the timing requirements associated with the distortion correction scheme (see the Timing Requirements for Distortion Correction Scheme table for timing parameters). The input to the LVDS channel should be either idle low, idle high, or should have clock or DC-balanced data transitions at 25 MHz / 50 Mbps or higher. Low frequency or DC-unbalanced data is not allowed. The distortion-correction scheme runs an internal calibration each time the LVDS channel transitions from an idle state to a data transmission state. The calibration runs for a period of tCALIB during which the LVDS channel output is held at logic high. This calibration is also run at power up. Lack of activity on the receive inputs for a period greater than tIDLE_OUT takes the channel to an uncalibrated state. If the communication protocol requires the channel to transition to the idle state, the idle-high or idle-low state must be held for at least duration of tIDLE.

ISO7821LLS td_dcd_correction_sllset5.gif
A. Signals shown are differential logic states.
Logic high → VIN+ > VIN–
Logic low → VIN– > VIN+
B. The data to ISOLVDS channel should be either idle high, idle low, clock, or valid data.
Valid data = 8b10b like data with DC balance and bounded disparity.
C. When transitioning from an uncalibrated sate to a calibrated state, the ISOLVDS channel output is gated high for up to tCALIB, during which the channel is calibrated.
D. If the channel finds no transitions in the incoming data for a period of tIDLE_OUT, the channel goes to an uncalibrated state.
E. Power loss (which implies no data transitions) takes the channel to an uncalibrated state.
F. If, for some reason, the idle-high or idle-low state must be held on the line, this state must be held for at least tIDLE.
Figure 25. DCD Correction Timing Diagram

8.4 Device Functional Modes

Table 2 lists the functional modes for the ISO7821LLS device.

Table 2. ISO7821LLS Function Table(1)

VCCI VCCO INPUT
(INx±)(2)		 OUTPUT ENABLE
(ENx) 		OUTPUT
(OUTx±)(3)		 COMMENTS
PU PU H H or open H Normal Operation:
A channel output assumes the logic state of the input.
L H or open L
I H or open H or L
X PU X L Z A low-logic state at the output enable causes the outputs to be in high impedance.
PD PU X H or open H Default mode: When VCCI is unpowered, a channel output assumes the logic high state.
When VCCI transitions from unpowered to powered up, a channel output assumes the logic state of the input.
When VCCI transitions from powered up to unpowered, a channel output assumes the selected default high state.
X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined.
When VCCO transitions from unpowered to powered up, a channel output assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCCx ≥ 2.25 V); PD = Powered down (VCCx ≤ 1.7 V); X = Irrelevant
(2) Input (INx±): H = high level (VID ≥ 50 mV); L = low level (VID ≤ –50 mV); I = indeterminate (–50 mV < VID < 50 mV)
(3) Output (OUTx±): H = high level (VOD ≥ 250 mV); L = low level (VOD ≤ –250 mV); Z = high impedance.

8.4.1 Device I/O Schematics

ISO7821LLS device_IO_sllset8.gif Figure 26. Device I/O Schematics