SLLSET5A March   2016  – September 2016 ISO7821LLS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  DC Electrical Characteristics
    10. 6.10 DC Supply Current Characteristics
    11. 6.11 Timing Requirements for Distortion Correction Scheme
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Distortion-Correction Scheme
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DW and DWW Packages
16-Pin SOIC
Top View
ISO7821LLS po_iso7821llx_sllset5.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN1 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high impedance state when EN1 is low.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high impedance state when EN2 is low.
GND1 2 — Ground connection for VCC1
8
GND2 9 — Ground connection for VCC2
15
INA+ 3 I Positive differential input, channel A
INA– 4 I Negative differential input, channel A
INB+ 11 I Positive differential input, channel B
INB– 12 I Negative differential input, channel B
OUTA+ 14 O Positive differential output, channel A
OUTA– 13 O Negative differential output, channel A
OUTB+ 6 O Positive differential output, channel B
OUTB– 5 O Negative differential output, channel B
VCC1 1 — Power supply, side 1, VCC1
VCC2 16 — Power supply, side 2, VCC2