SLLSEV7E August   2016  – March 2023 TUSB546-DCI

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 28
      3. 7.4.3 Device Configuration In I2C Mode
      4. 7.4.4 DisplayPort Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 USB3.1 Modes
      7. 7.4.7 Operation Timing – Power Up
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 7.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 7.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 7.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 7.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 7.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 7.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 7.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-EF916D7E-022A-46C5-99FB-9D44E26EFD27-low.svgFigure 5-1 RNQ Package,40-Pin WQFN(Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DP0p 9 Diff I DP Differential positive input for DisplayPort Lane 0.
DP0n 10 Diff I DP Differential negative input for DisplayPort Lane 0.
DP1p 12 Diff I DP Differential positive input for DisplayPort Lane 1.
DP1n 13 Diff I DP Differential negative input for DisplayPort Lane 1.
DP2p 15 Diff I DP Differential positive input for DisplayPort Lane 2.
DP2n 16 Diff I DP Differential negative input for DisplayPort Lane 2.
DP3p 18 Diff I DP Differential positive input for DisplayPort Lane 3.
DP3n 19 Diff I DP Differential negative input for DisplayPort Lane 3.
RX1n 31 Diff I/O Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port.
RX1p 30 Diff I/O Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port.
TX1n 34 Diff O Differential negative output for DisplayPort or USB3.1 downstream facing port.
TX1p 33 Diff O Differential positive output for DisplayPort or USB 3.1 downstream facing port.
TX2p 37 Diff O Differential positive output for DisplayPort or USB 3.1 downstream facing port.
TX2n 36 Diff O Differential negative output for DisplayPort or USB 3.1 downstream facing port.
RX2p 40 Diff I/O Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port.
RX2n 39 Diff I/O Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port.
SSTXp 8 Diff I Differential positive input for USB3.1 upstream facing port.
SSTXn 7 Diff I Differential negative input for USB3.1 upstream facing port.
SSRXp 5 Diff O Differential positive output for USB3.1 upstream facing port.
SSRXn 4 Diff O Differential negative output for USB3.1 upstream facing port.
EQ1 35 4 Level I This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Up to 11dB of EQ available.
EQ0 38 4 Level I This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Up to 11 dB of EQ available.
CAD_SNK/ RSVD1(1) 29 I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).
HPDIN/ RSVD2(1) 32 I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed.
I2C_EN 17 4 Level I I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled)
R = TI Test Mode (I2C enabled at 3.3 V)
F = I2C enabled at 1.8 V
1 = I2C enabled at 3.3 V.
SBU1 27 I/O, CMOS SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended.
SBU2 26 I/O, CMOS SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended.
AUXp 24 I/O, CMOS AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This pin along with AUXN is used by the TUSB546-DCI for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
AUXn 25 I/O, CMOS AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to DP_PWR (3.3V). This pin along with AUXP is used by the TUSB546-DCI for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
DPEQ1 2 4 Level I DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization gain.
DPEQ0/A1 14 4 Level I DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization gain. When I2C_EN is not ‘0’, this pin will also set the TUSB546-DCI I2C address.
SSEQ1 3 4 Level I Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N.
SSEQ0/A0 11 4 Level I Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin will also set the TUSB546-DCI I2C address. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
FLIP/SCL 21 2 Level I When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C controller's VCC I2C supply.
CTL0/SDA 22 2 Level I When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C controller's VCC I2C supply.
CTL1/HPDIN 23 2 Level I
(Failsafe)
(PD)		 DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink. When this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed.
VCC 1, 6, 20, 28 P 3.3-V Power Supply
Thermal Pad G Ground
(1) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.