SLLSEV7E August   2016  – March 2023 TUSB546-DCI

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.1
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 28
      3. 7.4.3 Device Configuration In I2C Mode
      4. 7.4.4 DisplayPort Mode
      5. 7.4.5 Linear EQ Configuration
      6. 7.4.6 USB3.1 Modes
      7. 7.4.7 Operation Timing – Power Up
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 7.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 7.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 7.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 7.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 7.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 7.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 7.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

7.5 Programming

For further programmability, the TUSB546-DCI can be controlled using I2C. The SCL and SDA pins are used for I2C clock and I2C data respectively.

Table 7-9 TUSB546-DCI I2C Target Address
DPEQ0/A1
PIN LEVEL		SSEQ0/A0
PIN LEVEL		Bit 7 (MSB)Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 (W/R)
0010001000/1
0R10001010/1
0F10001100/1
0110001110/1
R001000000/1
RR01000010/1
RF01000100/1
R101000110/1
F000100000/1
FR00100010/1
FF00100100/1
F100100110/1
1000011000/1
1R00011010/1
1F00011100/1
1100011110/1

The following procedure should be followed to write to TUSB546-DCI I2C registers:

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB546-DCI 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB546-DCI acknowledges the address cycle.
  3. The controller presents the sub-address (I2C register within TUSB546-DCI) to be written, consisting of one byte of data, MSB-first.
  4. The TUSB546-DCI acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TUSB546-DCI acknowledges the byte transfer.
  7. The controller may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB546-DCI.
  8. The controller terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TUSB546-DCI I2C registers:

  1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB546-DCI 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  2. The TUSB546-DCI acknowledges the address cycle.
  3. The TUSB546-DCI transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB546-DCI shall start at the sub-address specified in the write.
  4. The TUSB546-DCI shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  5. If an ACK is received, the TUSB546-DCI transmits the next byte of data.
  6. The controller terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

  1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB546-DCI 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TUSB546-DCI acknowledges the address cycle.
  3. The controller presents the sub-address (I2C register within TUSB546-DCI) to be written, consisting of one byte of data, MSB-first.
  4. The TUSB546-DCI acknowledges the sub-address cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note:

If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.

Table 7-10 Register Legend
ACCESS TAGNAMEMEANING
RReadThe field may be read by software
WWriteThe field may be written by software
SSetThe field may be set by a write of one. Writes of zeros to the field have no effect.
CClearThe field may be cleared by a write of one. Write of zero to the field have no effect.
UUpdateHardware may autonomously update this field.
NANo AccessNot accessible or not applicable