SLLSEX2F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics, Power Supply

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(2)MAX(1)UNIT
PD1Device power DissipationOE = H,VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 1200mV, 6Gbps TMDS pattern, VI = 3.3V, I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2 = H		200350mW
PD2Device power Dissipation in DP-ModeOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 400mV, 5.4Gbps DP pattern, I2C_EN = H, VOD = 400mV PRE = 0dB		330680mW
P(STBY1)Stage 1: Standby PowerOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V , HPD = H, No input Signal: Stage 1 See Section 8.3.234mW
Stage 2: Standby PowerOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V , HPD = H, Noise on input Signal: Stage 2 See Section 8.3.260mW
P(SD1)Device power in PowerDownOE = L, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V834mW
P(SD2)Device power in PowerDown in DP-ModeOE = L, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V834mW
ICC1VCC Supply currentOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 1200mV, 6Gbps TMDS pattern
I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2 = H,		820mA
ICC2VCC Supply current in DP-ModeOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 400mV, 5.4Gbps DP pattern, I2C_EN = H, VOD = 400mV PRE = 0dB		45110mA
IDD1VDD Supply currentOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 1200mV, 6Gbps TMDS pattern
I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2 = H		160220mA
IDD2VDD Supply current DP-ModeOE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V
IN_Dx: VID_PP = 400mV, 5.4Gbps DP pattern, I2C_EN = H, VOD = 40mV PRE =dB		160220mA
I(STBY1)Stage 1: Standby current See Section 8.3.2OE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V , HPD = H: No signal on IN_CLK3.3V Rail7mA
1.1V Rail7mA
Stage 2: Standby current See Section 8.3.2OE = H, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V , HPD = H: No valid signal on IN_CLK3.3V Rail7mA
1.1V Rail27mA
I(SD11)PowerDown current – HDMI ModeOE = L, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V , or OE = H, HPD = L3.3V Rail17mA
1.1V Rail47mA
I(SD2)PowerDown current in DP-ModeOE = L, VCC = 3.3V/3.6V, VDD = 1.1V/1.27V3.3V Rail17mA
1.1V Rail47mA
(1) The maximum rating is simulated at 3.6V VCC and 1.27V VDD and at 85°C temperature unless otherwise noted.
(2) The typical rating is simulated at 3.3V VCC and 1.1V VDD and at 27°C temperature unless otherwise noted.