SLLSEX2F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.12 DP-Mode Description

The TDP158 has the ability to perform as a DisplayPort redriver under the right conditions. The TDP158 is put into this mode by setting reg09h[5] to 1. The device is now programmable through I2C only. As the transmitter is a DC coupled transmitter supporting TMDS some external circuits are required to level shift the signal to an AC-coupled DisplayPort signal, see Figure 8-6. Note that the AUX lines bypass the TDP158. To set the device up correctly during link training, the TDP158 must be programmed using I2C. When this bit is set, the TDP158 does the following:

  • Ignore SWAP function
  • Ignore SIG_EN function
  • Enable all four lanes and set to support 5.4Gbps data rate
  • Sets VOD swing to the lowest level based on a 6 kΩ VSADJ resistor value
  • Sets pre-emphasis to 0dB
  • Defaults to global lane control
  • Can be set to independent lane control by setting P0_Reg09[6] to a 1. This should be done after implementing DP mode. Individual Lane control starts on P0_Reg30 through P0_Reg34 and also P0_Reg4E and 4F

For the system implementer to configure the TDP158 output to the properly requested levels during link training, the following registers are used.

  • Reg0Ch[7:5] is a global VOD swing control for all four lanes; Table 7-5 provides more information
  • Reg0Ch[1:0] is a global pre-emphasis control for all four lanes; Table 7-5 provides more information. This register works with Reg30h[7:6]
  • Reg0D[6:3] is a global EQ control for all four lanes
  • Reg30h[7:6] is to let the TDP158 know what the data rate is. This is used for the delay component for pre-emphasis signal.
  • Reg30h[5:2] is used to turn on or off individual lanes

Power down states while in DP-Mode are implemented the same as if in normal operation. See Section 5.7 for the outputs based upon the VSADJ 6kΩ VSADJ resistor.