6 Parameter Measurement Information

Figure 6-1 TMDS Main Link Test Circuit

Figure 6-2 Input or Output Timing Measurements

Figure 6-3 Output Differential Waveform

Figure 6-4 Output Differential Waveform with De-Emphasis

A. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling capacitor, connector and another 1-8” of FR4. Trace width – 4 mils. 100Ω differential impedance.

B. All Jitter is measured at a BER of 10⁹

C. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP

D. AVCC = 3.3V

E. R_T = 50Ω

F. The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.

Figure 6-5 HDMI Output Jitter Measurement

Figure 6-6 Output Eye Mask at TTP4_EQ for HDMI 2.0

TMDS Data Rate (Gbps)	H (Tbit)	V (mV)
3.4 < DR < 3.712	0.6	335
3.712 < DR < 5.94	–0.0332Rbit² + 0.2312 R_bit + 0.1998	–19.66Rbit² + 106.74R_bit + 209.58
5.94 ≤ DR ≤ 6.0	0.4	150

Figure 6-7 HPD Test Circuit

Figure 6-8 HPD Timing Diagram No. 1

Figure 6-9 HPD Logic Disconnect Timeout

Figure 6-10 Start and Stop Condition Timing

Figure 6-11 SCL and SDA Timing

Figure 6-12 DDC Propagation Delay – Source to Sink

Figure 6-13 DDC Propagation Delay – Sink to Source

Figure 6-14 V_ID(DC) and V_ID(EYE)