SLLSEX2F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

DDC Pull Up Resistors

This section is for information only and subject to change depending upon system implementation. The pull-up resistor value is determined by two requirements:

  1. The maximum sink current of the I2C buffer:

    The maximum sink current is 3mA or slightly higher for an I2C driver supporting standard-mode I2C operation.

    Equation 1. R U P   ( m i n ) =   V C C I s i n k

  2. The maximum transition time on the bus:

    The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pull-up resistor value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 8-2 provides the possible values of k under different threshold combinations.

    Equation 2. T = k   ×   R C
    Equation 3. V ( t ) = V D D   ×   ( 1 - e - t R C )
Table 8-2 Value k Upon Different Input Threshold Voltages
Vth-\Vth+0.7VCC0.65VCC0.6VCC0.55VCC0.5VCC0.45VCC0.4VCC0.35VCC0.3VCC
0.1VCC1.09860.94450.81090.69310.58780.49250.40550.32540.2513
0.15VCC1.04150.88730.75380.63600.53060.43530.34830.26830.1942
0.2VCC0.98080.82670.69310.57540.47000.37470.28770.20760.1335
0.25VCC0.91630.76210.62860.51080.40550.31020.22310.14310.0690
0.3VCC0.84730.69310.55960.44180.33650.24120.15420.0741

From Equation 1, Rup(min) = 5.5V/3mA = 1.83kΩ to operate the bus under a 5-V pull-up voltage and provide less than 3mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4mA, is allowed, Rup(min) can be as low as 1.375kΩ.

If DDC working at standard mode of 100Kbps, the maximum transition time T is fixed, 1 μs, and using the k values provided in Table 8-2, then the recommended maximum total resistance of the pull-up resistors on an I2C bus can be calculated for different system setups. If DDC working in fast mode of 400Kbps, the transition time should be set at 300 ns according to I2C specification.

To support the maximum load capacitance specified in the HDMI specification, C(cable)(max) = 700 pF, C(source) = 50 pF,
CI = 50 pF, R(max) can be calculated as provided in Table 8-3.

Table 8-3 Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads
Vth-\Vth+0.7VCC0.65VCC0.6VCC0.55VCC0.5VCC0.45VCC0.4VCC0.35VCC0.3VCCUNIT
0.1VCC1.141.321.541.82.132.543.083.844.97kΩ
0.15VCC1.21.411.661.972.362.873.594.666.44kΩ
0.2VCC1.271.511.82.172.663.344.356.029.36kΩ
0.25VCC1.361.641.992.453.084.035.68.7418.12kΩ
0.3VCC1.481.82.232.833.725.188.1116.87kΩ

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support a maximum 800-pF load capacitance for a standard-mode I2C bus.