SLLSEY0A April   2017  – July 2017 TPD2S701-Q1

PRODUCTION DATA.  

1. 1 Features
2. 2 Applications
3. 3 Description
4. 4 Revision History
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings—AEC Specification
   3. 6.3  ESD Ratings—IEC Specification
   4. 6.4  ESD Ratings—ISO Specification
   5. 6.5  Recommended Operating Conditions
   6. 6.6  Thermal Information
   7. 6.7  Electrical Characteristics
   8. 6.8  Power Supply and Supply Current Consumption Chracteristics
   9. 6.9  Timing Requirements
   10. 6.10 Typical Characteristics
7. 7 Parameter Measurement Information
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
   4. 8.4 Device Functional Modes
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
         1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
         1. 9.2.2.1 VREF Operation
            1. 9.2.2.1.1 Mode 0
            2. 9.2.2.1.2 Mode 1
         2. 9.2.2.2 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
12. 12Device and Documentation Support
    1. 12.1 Documentation Support
       1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
13. 13Mechanical, Packaging, and Orderable Information