SLLSF10 December 2019 TL16C750E
PRODUCTION DATA.
This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows the enhanced feature register bit settings.
BIT | BIT SETTINGS |
---|---|
3:0 | Combinations of software flow control can be selected by programming bit 3 to bit 0. See Table 6. |
4 | Enhanced functions enable bit.
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5] 1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a write enable |
5 | 0 = Normal operation
1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected. |
6 | RTS flow control enable bit
0 = Normal operation 1 = RTS flow control is enabled, that is, RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached. |
7 | CTS flow control enable bit
0 = Normal operation 1 = CTS flow control is enabled, that is, transmission is halted when a high signal is detected on the CTS pin |