SLLSF22H April   2018  – June 2024 ISO1410 , ISO1412 , ISO1430 , ISO1432 , ISO1450 , ISO1452

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Description Continued
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions: Full-Duplex Device
    2.     Pin Functions: Half-Duplex Device
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: Driver
    10. 7.10 Electrical Characteristics: Receiver
    11. 7.11 Supply Current Characteristics: Side 1 (ICC1)
    12. 7.12 Supply Current Characteristics: Side 2 (ICC2)
    13. 7.13 Switching Characteristics: Driver
    14. 7.14 Switching Characteristics: Receiver
    15. 7.15 Insulation Characteristics Curves
    16. 7.16 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Electromagnetic Compatibility (EMC) Considerations
      2. 9.3.2 Failsafe Receiver
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Glitch-Free Power Up and Power Down
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data Rate and Bus Length
        2. 10.2.2.2 Stub Length
        3. 10.2.2.3 Bus Loading
      3. 10.2.3 Application Curves
        1. 10.2.3.1 Insulation Lifetime
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
        1. 13.1.1.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information

Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 12-2). Layer stacking must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

Section 12.2 shows the recommended placement and routing of the device bypass capacitors and optional TVS diodes. Put the VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep the it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Refer to the Digital Isolator Design Guide for detailed layout recommendations.