SLLSF28C December 2018 – June 2022 TLIN2441-Q1
PRODUCTION DATA
The following tables contain the registers that the device use during SPI communication
ADDRESS | REGISTER | VALUE | ACCESS |
---|---|---|---|
‘h00 | Reserved | 54 | R |
‘h01 | Reserved | 43 | R |
‘h02 | Reserved | 41 | R |
‘h03 | Reserved | 4E | R |
‘h04 | Reserved | 32 | R |
‘h05 | DEVICE_ID[7:0] "4" | 34 | R |
‘h06 | DEVICE_ID[7:0] "4" | 34 | R |
‘h07 | DEVICE_ID[7:0] "1" | 31 | R |
‘h08 | DEVICE_ID[7:0] “3” "5" | 33,35 | R |
‘h09 | Rev_ID Major | 01 | R |
‘h0A | REV_ID Minor | 00 | R |
ADDRESS | BIT(S) | DEFAULT | DESCRIPTION | ACCESS |
---|---|---|---|---|
'h0B | 7:6 | 2'b00 | MODE: Modes of Operation
00 = Standby Mode 01 = Sleep Mode 10 = Normal Mode 11 = Reserved | R/W/U |
5 | 1'b0 | LIMP_DIS: LIMP Disable
0 = LIMP Enabled 1 = LIMP Disabled | R/W/U | |
4:3 | 2'b00 | LIMP_SEL_RESET: Selects the method LIMP is reset/turned off
00 = On the third successful input trigger the error counter receives 01 = First correct input trigger 10 = SPI write 1 to h'0B[2] 11 = Reserved | R/W | |
2 | 1'b0 | LIMP Reset - Writing a one resets LIMP but then clears | R/WC | |
1 | 1'b0 | FAILSAFE_EN: Fail safe mode enable
0 = Disabled 1 = Enabled | R/W | |
0 | 1'b0 | DTO_DIS: Dominant timeout Disable
0 = DTO Enabled 1 = DTO Disabled | R/W | |
'h0C | 7 | 1'b0 | DTO Interrup | R/WC |
6 | 1'b0 | UVCC Interrupt | R/WC | |
5 | 1'b0 | TSD Interrupt | R/WC | |
4 | 1'b0 | SPIERR Interrupt | R/WC | |
3 | 1'b0 | WDERR Interrupt | R/WC | |
2 | 1'b0 | OVCC Interrupt | R/WC | |
1 | 1'b0 | LWU Interrupt | R/WC | |
0 | 1'b0 | WUP Interrupt | R/WC | |
'h0D | 7:0 | 8'h00 | Reserved | R |
'h0E | 7 | 1'b1 | DTO Interrupt Mask | R/W |
6 | 1'b1 | UVCC Interrupt Mask | R/W | |
5 | 1'b1 | TSD Interrupt Mask | R/W | |
4 | 1'b1 | SPIERR Interrupt Mask | R/W | |
3 | 1'b1 | WDERR Interrupt Mask | R/W | |
2 | 1'b1 | OVCC Interrupt Mask | R/W | |
1 | 1'b1 | LWU Interrupt Mask | R/W | |
0 | 1'b1 | WUP Interrupt Mask | R/W | |
'h0F | 7:0 | 8'h00 | Reserved | R |
'h10 | 7:4 | 4'b0000 | Reserved | R |
3:2 | 1'b0 | nRST_nWDR_SEL: Pin 12 configuration select when in SPI mode.
00 = nRST (Default) 01 = nWDR 10 = Both nRST for UVCC and nWDR for watchdog failure event 11 = Reserved | R/W | |
1 | 1'b0 | Reserved | R | |
0 | 1'b0 | SOFT_RST: Soft reset of device. Writing a 1 resets the registers to default values | R/WC |
ADDRESS | BIT(S) | DEFAULT | DESCRIPTION | ACCESS |
---|---|---|---|---|
'h11 | 7:0 | 8'h00 | Read and Write Capable Scratch Pad | R/W |
'h12 | 7:0 | 8'h00 | Read and Write Capable Scratch Pad | R/W |
'h13 | 7 | 1'b0 | WD_DIS - Watchdog Function Disable
0 = Enabled 1 = Disabled | R/W |
6 | 1'b0 | WD_WINDOW_TIMEOUT_SEL: Configures Watchdog as either a Window or Time-out watchdog
0 = Window 1 = Timeout | R/W | |
5:4 | 2'b00 | WD_PRE: Watchdog prescalar
00 = Factor 1 01 = Factor 2 10 = Factor 3 11 = Factor 4 | R/W | |
3:2 | 2'b00 | WD_ERR_CNT_SET Sets the watchdog event error counter that upon overflow the watchdog output trigger event taked place. Increases with each error and decreases with each correct WD trigger. Does not go below zero.
00 = Immediate trigger on each WD event 01 = 2-Bit: Triggers on the fifth error event 10 = 3-Bit: Triggers on the ninth error event 11 = Reserved | R/W | |
1:0 | 2'b10 | WD_ACTION: Selection Action when Watchdog times out or misses a window
00 = nINT is pulled low 01 = VCC is turned off for 100 ms and turned back on 10 = nWDR is toggled high → low → high 11 = Reserved | R/W | |
'h14 | 7:5 | 3'b000 | WD_TIMER - Sets the window or timeout times and is based upon the WD_PRE setting - See Table 9-3 | R/W |
4:1 | 4'b0100 | WD_ERR_CNT: Watchdog error counter: Keeps a running count of the errors up to 15 errors | R | |
0 | 1'b0 | Reserved | R | |
'h15 | 7:0 | 8'h00 | WD_TRIG: Writes to these bits resets the watchdog timer (FF) | WC |
For WD_ACTION turning off VCC for 100 ms and turning it back on, causes SPI communication to stop during the off time.