SLLSF47D February 2018 – April 2024 TUSB1044
PRODUCTION DATA
Table 6-10 lists the memory-mapped registers for the TUSB1044. All register offset addresses not listed in Table 6-10 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
Ah | General_1 | General Registers 1 | Go |
Bh | General_2 | General Registers 2 | Go |
Ch | General_3 | General Registers 3 | Go |
10h | UFP2_EQ | UFP2 EQ Control | Go |
11h | UFP1_EQ | UFP1 EQ Control | Go |
12h | DisplayPort_1 | AUX Snoop Status | Go |
13h | DisplayPort_2 | DP Lane Enable/Disable Control | Go |
1Bh | SOFT_RESET | I2C and DPCD Soft Resets | Go |
20h | DFP2_EQ | DFP2 EQ Control | Go |
21h | DFP1_EQ | DFP1 EQ Control | Go |
22h | USB3_MISC | Misc USB3 Controls | Go |
23h | USB3_LOS | USB3 LOS Threshold Controls | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-11 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | H R | Set or cleared by hardware Read |
Write Type | ||
H | H | Set or cleared by hardware |
W | W | Write |
WSH | H W WS | Set or cleared by hardware Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
General_1 is shown in Figure 6-1 and described in Table 6-12.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SWAP_SEL | EQ_OVERRIDE | HPDIN_OVERRIDE | FLIP_SEL | CTLSEL[1:0] | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | SWAP_SEL | R/W | 0h | Setting this field performs a global direction swap on all the channels. 0h = Channel directions and EQ settings are in normal mode 1h = Reverse all channel directions and EQ settings for the input ports. |
4 | EQ_OVERRIDE | R/W | 0h | Setting this field will allow software to use EQ settings from registers instead of value sampled from pins. 0h = EQ settings based on sampled state of EQ pins. 1h = EQ settings based on programmed value of each of the EQ registers. |
3 | HPDIN_OVERRIDE | R/W | 0h | Overrides HPDIN pin state. 0h = HPD_IN based on HPD_IN pin. 1h = HPD_IN high. |
2 | FLIP_SEL | R/W | 0h | FLIPSEL 0h = Normal Orientation 1h = Flip orientation. |
1-0 | CTLSEL[1:0] | R/W | 1h | Controls the DP and USB modes. 0h = Disabled. All RX and TX for USB3 and DisplayPort are disabled. 1h = USB3.1 only enabled. 2h = Four Lanes of DisplayPort enabled. 3h = USB3.1 and Two DisplayPort Lanes. |
General_2 is shown in Figure 6-2 and described in Table 6-13.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH_SWAP_SEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | Reserved |
3-0 | CH_SWAP_SEL | R/W | 0h | Swaps direction (TX to Rx and Rx to Tx) and EQ settings of individual channels. Channels are numbered from 0 to 3. 1 bit per lane. 0h = Channel and EQ settings normal. 1h = Reverse channel direction and EQ setting. |
General_3 is shown in Figure 6-3 and described in Table 6-14.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VOD_DCGAIN_OVERRIDE | VOD_DCGAIN_SEL | DIR_SEL | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6 | VOD_DCGAIN_OVERRIDE | R/W | 0h | Setting of this field will allow software to use VOD linearity range and DC gain settings from registers instead of value sampled from pins 0h = VOD linearity and DC gain settings based on sampled CFG[2:1] pins. 1h = EQ settings based on programmed value of each VOD linearity and DC Gain registers. |
5-2 | VOD_DCGAIN_SEL | R/W | 0h | Field selects VOD linearity range and DC gain for all the channels and in all directions. When VOD_DCGAIN_OVERRIDE = 0b, this field reflects the sampled state of CFG[1:0] pins. When VOD_DCGAIN_OVERRIDE = 1b software can change the VOD linearity range and DC gain for all the channels and in all directions based on value written to this field. Each CFG is a 2-bit value. The register-to-CFG1/0 mapping is: [5:2] = {CFG1[1:0], CFG0[1:0]} where CFGx[1:0] mapping is: 0h = 0 1h = R 2h = F 3h = 1 |
1-0 | DIR_SEL | R/W | 0h | Sets the operation mode. 0h = USB + DP Alt Mode Source 1h = USB + DP Alt Mode Sink. 2h = USB + Custom Alt Mode Source 3h = USB + Custom Alt Mode Sink. |
UFP2_EQ is shown in Figure 6-4 and described in Table 6-15.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTX2EQ_SEL | URX2EQ_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | UTX2EQ_SEL | R/W | 0h | Field selects EQ for UTX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for UTX2P/N pins based on value written to this field. |
3-0 | URX2EQ_SEL | R/W | 0h | Field selects EQ for URX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for URX2P/N pins based on value written to this field. |
UFP1_EQ is shown in Figure 6-5 and described in Table 6-16.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UTX1EQ_SEL | URX1EQ_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | UTX1EQ_SEL | R/W | 0h | Field selects EQ for UTX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for UTX1P/N pins based on value written to this field. |
3-0 | URX1EQ_SEL | R/W | 0h | Field selects EQ for URX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of UEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for URX1P/N pins based on value written to this field. |
DisplayPort_1 is shown in Figure 6-6 and described in Table 6-17.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SET_POWER_STATE | LANE_COUNT_SET | |||||
R-0h | RH-0h | RH-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6-5 | SET_POWER_STATE | RH | 0h | This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 0b, the enable/disable of DP lanes based on the snooped value. When AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b. |
4-0 | LANE_COUNT_SET | RH | 0h | This field represents the snooped value of AUX write to DPCD address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP lanes enabled specified by the snoop value. Unused DP lanes will be disabled to save power. When AUX_SNOOP_DISABLE = 1b, then DP lanes enable/disable are determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b. |
DisplayPort_2 is shown in Figure 6-7 and described in Table 6-18.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUX_SNOOP_DISABLE | RESERVED | AUX_SBU_OVR | DP3_DISABLE | DP2_DISABLE | DP1_DISABLE | DP0_DISABLE | |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | AUX_SNOOP_DISABLE | R/W | 0h | Controls whether DP lanes are enabled based on AUX snooped value or registers. 0h = AUX snoop enabled. 1h = AUX snoop disabled. DP lanes are controlled by registers. |
6 | RESERVED | R | 0h | Reserved |
5-4 | AUX_SBU_OVR | R/W | 0h | This field overrides the AUXP/N to SBU1/2 connect and disconnect based on CTL1 and FLIP. Changing this field to 1b will allow traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register. 0h = AUX to SBU connection determined by CTLSEL1 and FLIPSEL 1h = AUXP -> SBU1 and AUXN -> SBU2 2h = AUXP -> SBU2 and AUXN -> SBU1 3h = AUX to SBU open. |
3 | DP3_DISABLE | R/W | 0h | When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 0b, changes to this field will have no effect on lane 3 functionality. 0h = DP Lane 3 enabled. 1h = DP Lane 3 disabled. |
2 | DP2_DISABLE | R/W | 0h | When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 0b, changes to this field will have no effect on lane 2 functionality. 0h = DP Lane 2 enabled. 1h = DP Lane 2 disabled. |
1 | DP1_DISABLE | R/W | 0h | When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 0b, changes to this field will have no effect on lane 1 functionality. 0h = DP Lane 1 enabled. 1h = DP Lane 1 disabled. |
0 | DP0_DISABLE | R/W | 0h | When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes to this field will have no effect on lane 0 functionality. 0h = DP Lane 0 enabled. 1h = DP Lane 0 disabled. |
SOFT_RESET is shown in Figure 6-8 and described in Table 6-19.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2C_RST | DPCD_RST | RESERVED | |||||
RH/WS-0h | RH/WS-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | I2C_RST | RH/WS | 0h | Resets I2C registers to default values. This field is self-clearing. |
6 | DPCD_RST | RH/WS | 0h | Resets DPCD registers to default values. This field is self-clearing. |
5-0 | RESERVED | R | 0h | Reserved |
DFP2_EQ is shown in Figure 6-9 and described in Table 6-20.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DTX2EQ_SEL | DRX2EQ_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DTX2EQ_SEL | R/W | 0h | Field selects EQ for DTX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DTX2P/N pins based on value written to this field. |
3-0 | DRX2EQ_SEL | R/W | 0h | Field selects EQ for DRX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DRX2P/N pins based on value written to this field. |
DFP1_EQ is shown in Figure 6-10 and described in Table 6-21.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DTX1EQ_SEL | DRX1EQ_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | DTX1EQ_SEL | R/W | 0h | Field selects EQ for DTX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DTX1P/N pins based on value written to this field. |
3-0 | DRX1EQ_SEL | R/W | 0h | Field selects EQ for DRX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DRX1P/N pins based on value written to this field. |
USB3_MISC is shown in Figure 6-11 and described in Table 6-22.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CM_ACTIVE | LFPS_EQ | U2U3_LFPS_DEBOUNCE | DISABLE_U2U3_RXDET | DFP_RXDET_INTERVAL | USB_COMPLIANCE_CTRL | ||
RH-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CM_ACTIVE | RH | 0h | Compliance mode status. 0h = Not in USB3.1 compliance mode. 1h = In USB3.1 compliance mode. |
6 | LFPS_EQ | R/W | 0h | Controls whether settings of EQ based on URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies to received LFPS signal. 0h = EQ set to zero when receiving LFPS 1h = EQ set by the related registers when receiving LFPS. |
5 | U2U3_LFPS_DEBOUNCE | R/W | 0h | Controls whether or not incoming LFPS is debounced or not. 0h = No debounce of LFPS before U2/U3 exit. 1h = 200us debounce of LFPS before U2/U3 exit. |
4 | DISABLE_U2U3_RXDET | R/W | 0h | Controls whether or not Rx.Detect is performed in U2/U3 state. 0h = Rx.Detect in U2/U3 enabled. 1h = Rx.Detect in U2/U3 disabled. |
3-2 | DFP_RXDET_INTERVAL | R/W | 1h | This field controls the Rx.Detect interval for the downstream facing port (DTX1P/N and DTX2P/N). 0h = 8ms 1h = 12ms 2h = Reserved 3h = Reserved. |
1-0 | USB_COMPLIANCE_CTRL | R/W | 0h | Controls whether compliance mode is determined by FSM or register. 0h = Compliance mode determined by FSM. 1h = Compliance mode enabled in DFP direction. 2h = Compliance mode enabled in UFP direction. 3h = Compliance mode disabled. |
USB3_LOS is shown in Figure 6-12 and described in Table 6-23.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CFG_LOS_HYST | CFG_LOS_VTH | |||||
R-0h | R/W-4h | R/W-3h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5-3 | CFG_LOS_HYST | R/W | 4h | Controls LOS hysteresis defined as 20 log (LOS de-assert threshold/LOS assert threshold). 0h = 0.15 dB 1h = 0.85 dB 2h = 1.45 dB 3h = 2.00 dB 4h = 2.70 dB 5h = 3.00 dB 6h = 3.40 dB 7h = 3.80 dB |
2-0 | CFG_LOS_VTH | R/W | 3h | Controls LOS assert threshold voltage 0h = 67 mV 1h = 72 mV 2h = 79 mV 3h = 85 mV 4h = 91 mV 5h = 97 mV 6h = 105 mV 7h = 112 mV |