SLLSF63C March   2018  – July 2024 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Adjustable VOD Linear Range and DC Gain
      4. 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 6.3.7 Basic Redriver Operation (MODE = “0”)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
    5. 6.5 U0 Mode
    6. 6.6 U1 Mode
    7. 6.7 U2/U3 Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical USB3.2 Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 ESD Protection
      4. 7.2.4 Application Curves
    3. 7.3 Typical SATA, PCIe and SATA Express Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1 Design Requirements

For this design example, use the parameters shown in Table 7-1.

Table 7-1 Design Parameters
PARAMETER VALUE
Pre-channel A to B PCB trace length(1), LAB. 1 inches ≤ LAB ≤ 12 inches - LCD
Post-channel C to D PCB trace length(1), LCD. ≤ 4 inches
Minimum distance of the AC capacitors from TUSB1002A, LAC-CAP 0.25 inches
Maximum distance of ESD component from the USB receptacle, LESD 0.6 inches
Maximum distance of series resistor (RESD) from ESD component, LR_ESD. 0.25 inches
CAC-USB1 AC-coupling capacitor (75nF to 265nF) 220nF
CAC-USB2 AC-coupling capacitor (297nF to 363nF) Options:
  • RX1 and RX2 are DC-coupled to USB receptacle
  • 330nF AC-couple with RRX resistor
Optional RRX resistor (220kΩ ± 5%) No used
Optional RESD (0Ω to 2.2Ω) 1Ω
VCC supply (3V to 3.6-V) 3.3V
Mode of Operation (Dual or Half Channel) MODE = F (Floating) for USB3.2 Dual Channel
Linear Range (900mV, 1000mV, or 1200 mV) 1200mV (CFG[2:1] pins floating)
DC Gain (-2, -1, 0, +1, +2) 0dB (CFG[2:1] pins floating)
(1) Maximum trace length assumes an insertion loss of 0.2dB/inch/GHz. If insertion loss is more than 0.2 dB/inch/GHz, then maximum trace length must be reduced accordingly.