SLLSF63C March 2018 – July 2024 TUSB1002A
PRODUCTION DATA
PIN | TYPE | INTERNAL PULLUP PULLDOWN | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
RX1P | 9 | 90Ω Differential Input | — | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1 |
RX1N | 8 | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1 | ||
RX2P | 19 | 90Ω Differential Input | — | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2 |
RX2N | 20 | Differential input for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2. | ||
TX1P | 22 | 90Ω Differential Output | — | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 1. |
TX1N | 23 | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 1. | ||
TX2P | 12 | 90Ω Differential Output | — | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) positive signals for Channel 2. |
TX2N | 11 | Differential output for SuperSpeed (SS) and SuperSpeedPlus (SSP) negative signals for Channel 2. | ||
CH1_EQ1 | 2 | I (4-level) | PU (approx 45K) PD (approx 95K) |
CH1_EQ1. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings. |
CH1_EQ2 | 3 | I (4-level) | CH1_EQ2. Configuration pin used to control Rx EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings. | |
CH2_EQ1 | 16 | I (4-level) | CH2_EQ1. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings. | |
CH2_EQ2 | 17 | I (4-level) | CH2_EQ2. Configuration pin used to control Rx EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings. | |
EN | 5 | I (2-level) | PU (approx 400 K) | EN. Places TUSB1002A into shutdown mode when asserted low. Normal operation when pin is asserted high. When in shutdown, TUSB1002A’s receiver terminations are high impedance and tx/rx channels are disabled. |
CFG1 | 4 | I (4-level) | PU (approx 45K) PD (approx 95K) |
CFG1. This pin along with CFG2 selects the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options. |
CFG2 | 15 | I (4-level) | PU (approx 45K) PD (approx 95K) |
CFG2. This pin along with CFG1 sets the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options. |
MODE | 7 | I (4-level) | PU (approx 45 K) PD (approx 95K) |
MODE. This pin is for selecting different modes of operation. The
state of this pin is sampled after the rising edge of EN. Refer to
Figure 5-2 for details of timing. 0 = Basic Redriver Mode. R = PCIe / Test Mode. PCIe Mode and TI Internal use only F = USB3.2 x1 Dual Channel Operation enabled (TUSB1002A normal mode). 1 = USB3.2 x1 Single-channel operation. |
RSVD1 | 24 | O | — | RSVD1. Under normal operation, this pin is driven low by TUSB1002A. Recommend leaving this pin unconnected on PCB. |
DCBOOST# | 14 | I (2-level) | PU (approx 400 K) | DCBOOST#. This pin when asserted low increases the DC Gain level
defined inTable 6-3 by +1dB unless already at +2dB. If DC Gain level defined inTable 6-3 is already at +2dB, then asserting this pin low will not change
the DC Gain level. This pin can be left unconnected if this function
is not needed. 1 = DC Gain defined by Table 6-3. 0 = DC Gain defined by Table 6-3 is increased by +1dB. |
VCC | 1, 13 | Power | — | 3.3V (±10%) Supply. |
GND | 6, 10, 18, 21 | GND | — | Ground |
Thermal pad | — | Thermal pad. Recommend connecting to a solid ground plane. |