SLLSF63C March   2018  – July 2024 TUSB1002A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Adjustable VOD Linear Range and DC Gain
      4. 6.3.4 USB3.2 Dual Channel Operation (MODE = “F”)
      5. 6.3.5 USB3.2 Single Channel Operation (MODE = “1”)
      6. 6.3.6 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
      7. 6.3.7 Basic Redriver Operation (MODE = “0”)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
    5. 6.5 U0 Mode
    6. 6.6 U1 Mode
    7. 6.7 U2/U3 Mode
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical USB3.2 Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 ESD Protection
      4. 7.2.4 Application Curves
    3. 7.3 Typical SATA, PCIe and SATA Express Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curves
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Detailed Design Procedure

The TUSB1002A differential receivers and transmitters have internal BIAS and termination. For this reason, the TUSB1002A must be connected to the USB3.2 host and receptacle through external A/C coupling capacitors. In this example 220nF capacitors are placed on TX2P and TX2N, RX1P and RX1N, and TX1P and TX1N. 330nF A/C coupling capacitors along with 220kΩ resistors to ground are placed on the RX2P and RX2N. Inclusion of the 330nF capacitors and 220k resistors is optional. The ordered list below details the three implementation options for the RX2p/n path.

There are three implementation options for USB connector to the TUSB1002A RX pins:

  1. DC couple the TUSB1002A RX pins to USB connector. No 330nF capacitors and no 220kΩ pulldown resistors.
  2. 330nF capacitors with 220kΩ resistors as shown in Figure 7-2. The purpose of 220kΩ resistors is to discharge the capacitor within 250ms after a USB device is removed from the USB connector.
  3. The stub from the 220kΩ resistor pad may create impedance discontinuities causing negative impact to performance. Assuming leakage current from external components is enough to discharge capacitor, 330nF capacitor without the 220kΩ resistor is a valid option.

TUSB1002A Host
                    Implementation Schematic Figure 7-2 Host Implementation Schematic

The USB3.2 Dual channel operation is used in this example. Leave the mode pin floating (unconnected) when using this mode.

The TUSB1002A compensates for channel loss in both the upstream (D to C) and downstream direction (A to B). This is done by configurable the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as close possible to the channel insertion loss. In this particular example, CH1_EQ[2:1] is for path A to B which is the channel between USB3.2 host and the TUSB1002A, and CH2_EQ[2:1] is for path C to D which is the channel between TUSB1002A and the USB3.2 receptacle.

The TUSB1002A supports five levels of DC gain that are selected by the CFG[2:1] pins. Typically, the DC gain is set to 0dB but may need to be adjusted to correct any one of the following conditions:

  1. Input VID too high resulting in VOD being greater than USB 3.2 defined swing. For this case, use a negative DC gain.
  2. Input VID too low resulting in VOD being less than USB 3.2 defined swing. For this case, use a positive DC gain.
  3. Low frequency discontinuities in the channel resulting in DC component of the signal clipping the vertical eye mask. For this case, use a positive DC gain.

Assume in this example that the incoming VID is at the nominal defined USB3.2 range and the channel is linear across frequency. The CFG1 and CFG2 pins can both be left floating if these assumptions are true.

In this particular example, the channel A-B has a trace length of 8 inches with a 4mil trace width. This particular channel has about 0.83dB per inch of insertion loss at 5GHz. This equates to approximately 6.7dB of loss for the entire 8 inches of trace. An additional 1.5dB of loss is added due to package of the USB3.2 Host, TUSB1002A, and the A/C coupling capacitor. This brings the entire channel loss at 5GHz to 6.7dB + 1.5dB = 8.2dB. A typical USB 3.1 host/device has around 3dB of transmitter de-emphasis. Transmitter de-emphasis pre-compensates for the loss of the output channel. With 3dB of de-emphasis, the total equalization required by the TUSB1002A is in the 5.2dB (8.2dB - 3dB) range. The channel A-B for this example is connected to the RX1P/N input of the device, therefore the CH1_EQ[2:1] pins are used to adjust the TUSB1002A RX1P/N equalization settings. Set the CH1_EQ[2:1] pins such that the TUSB1002A equalization is between 5dB and 8dB.

The channel C-D has a trace length of 2 inches with a 4mil trace width. Assuming 0.83dB per inch of insertion loss, the 2 inch trace equates to about 1.66dB of loss at 5GHz. An additional 2dB of loss needs to be added due to package, A/C coupling capacitor, and the USB 3.1 receptacle. The total loss is around 3.66dB. Because channel C-D includes a USB 3.1 receptacle, the actual total loss can be much greater than 3.66dB due to the fact that devices plugged into the receptacle will also have loss. The device plugged into receptacle will have either a short or long channel. USB3.2 standard defines total loss limit of 23dB that is distributed as 8.5dB for Host, 8.5dB for device, and 6.0dB for cable. With variable channel of devices plugged into the USB3.2 receptacle, the configurable TUSB1002A RX2P/N equalization settings is not as straight forward as Channel A-B.

Engineer can not set TUSB1002A CH2_EQ[2:1] pins to the largest equalization setting to accommodate the largest allowed USB3.2 device/cable loss of 14.5dB, because doing so will cause the TUSB1002A to operate outside its linear range when a device with short channel is plugged into the receptacle. For this reason, TI recommends configure the TUSB1002A CH2_EQ[2:1] pins to equalize a shorter device channel, which will require the USB3.2 host to compensate for remaining channel loss for the worse case USB3.2 channel of 14.5dB. The definition of a short device channel is not specified in USB 3.2 specification. Therefore, an engineer must make their own loss estimate of what constitutes a short device channel. For particular example, assume the short channel is around 2 to 3dB. The channel loss of the device must be added to the estimated Channel C-D loss minus the typical 3dB of de-emphasis. This means CH2_EQ[2:1] pins can be configured to handle a loss of 3dB to 5dB.