SLLSFF7A may   2021  – december 2021 ISOW1044

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Description Continued
  7. Device Comparison Table
  8. Pin Configuration and Functions
  9. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  ThermalInformation
    5. 8.5  Power Ratings
    6. 8.6  Insulation Specifications
    7. 8.7  Safety-Related Certifications
    8. 8.8  Safety Limiting Values
    9. 8.9  Electrical Characteristics
    10. 8.10 Supply Current Characteristics
    11. 8.11 Switching Characteristics
    12. 8.12 Insulation Characteristics Curves
    13. 8.13 Typical Characteristics
  10. Parameter Measurement Information
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Power Isolation
    3. 10.3 Signal Isolation
    4. 10.4 CAN Transceiver
      1. 10.4.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
    5. 10.5 Functional Block Diagram
    6. 10.6 Feature Description
      1. 10.6.1 CAN Bus States
      2. 10.6.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 10.6.3 TXD Dominant Timeout (DTO)
      4. 10.6.4 Power-Up and Power-Down Behavior
      5. 10.6.5 Protection Features
      6. 10.6.6 Floating Pins, Unpowered Device
      7. 10.6.7 Glitch-Free Power Up and Power Down
    7. 10.7 Device Functional Modes
    8. 10.8 Device I/O Schematics
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Bus Loading, Length and Number of Nodes
        2. 11.2.2.2 CAN Termination
      3. 11.2.3 Application Curve
      4. 11.2.4 Insulation Lifetime
  13. 12Power Supply Recommendations
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  16. 15Mechanical, Packaging, and Orderable Information

Layout Guidelines

Figure 11-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must be followed to achieve low emissions design:

  1. High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, within 1 mm distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure that these capacitors are 0402 size so that they offer least inductance (ESL).
  2. Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply pins after the 10 nF capacitor with a distance of 2 - 4 mm, as shown in Layout Example.
  3. Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2 must be symmetric.
  4. Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply pins, one between VISOOUT and VISOIN and the other between GND2 (pin 11) and GND2(pin 15), as shown in example PCB layout, so that any high frequency noise from power converter output sees a high impedance before it goes to other components on PCB.
  5. Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT (pin12) and GND2 (pin11).
  6. Place the CAN BUS protection and filtering circuitry close to the bus connector to prevent transients, ESD, and noise from propagating onto the board. This layout example shows an optional transient voltage suppression (TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of the transceiver. This example also shows two optional 68pF bus filter capacitors
  7. Common mode choke or ferrite beads on bus terminals (CANH/CANL) can minimise any high frequency noise that can couple of CAN bus cable which can act as antenna and amplify that noise. This will improve Radiated emissions performance on a system level.
  8. Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated emissions design. EVM Link is available in Related Documentation.