SLLSFF7A may   2021  – december 2021 ISOW1044

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description Continued
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  ThermalInformation
    5. 8.5  Power Ratings
    6. 8.6  Insulation Specifications
    7. 8.7  Safety-Related Certifications
    8. 8.8  Safety Limiting Values
    9. 8.9  Electrical Characteristics
    10. 8.10 Supply Current Characteristics
    11. 8.11 Switching Characteristics
    12. 8.12 Insulation Characteristics Curves
    13. 8.13 Typical Characteristics
  10. 9 Parameter Measurement Information
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Power Isolation
    3. 10.3 Signal Isolation
    4. 10.4 CAN Transceiver
      1. 10.4.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
    5. 10.5 Functional Block Diagram
    6. 10.6 Feature Description
      1. 10.6.1 CAN Bus States
      2. 10.6.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 10.6.3 TXD Dominant Timeout (DTO)
      4. 10.6.4 Power-Up and Power-Down Behavior
      5. 10.6.5 Protection Features
      6. 10.6.6 Floating Pins, Unpowered Device
      7. 10.6.7 Glitch-Free Power Up and Power Down
    7. 10.7 Device Functional Modes
    8. 10.8 Device I/O Schematics
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Bus Loading, Length and Number of Nodes
        2. 11.2.2.2 CAN Termination
      3. 11.2.3 Application Curve
      4. 11.2.4 Insulation Lifetime
  13. 12Power Supply Recommendations
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  16. 15Mechanical, Packaging, and Orderable Information

8.11 Switching Characteristics

Typical specifications are at VIO = 3.3V, VDD = 5V, GND1 = GNDIO, GND2 = GISOIN, Min/Max are over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1) Total loop delay, driver input TXD to receiver RXD, recessive to dominant RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD = 1 ns; 1.71 V < VIO < 5.5 V, See Figure 9-3 140 205 ns
tPROP(LOOP2) Total loop delay, driver input TXD to receiver RXD, dominant to recessive RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V < VIO <5.5 V, See Figure 9-3 167 222 ns
tMODE Mode change time, from Normal to Standby or from Standby to Normal 20 us
tWK_FILTER Filter time for a valid wake-up pattern 0.5 1.8 us
tWK_TIMEOUT Bus wake-up timeout value 0.8 5 ms
CMTI Common mode transient immunity TXD = VIO or GND1, VCM = 1200 VPK, See Figure 9-9 85 100 kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHR Propagation delay time, LOW to HIGH TXD edge to driver recessive (dominant to recessive) RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns, See Figure 9-3 87 110 ns
tpLD Propagation delay time, HIGH TO LOW TXD edge to driver dominant (recessive to dominant) 78 105
tsk(p) pulse skew (|tpHR - tpLD|) 15
tR Differential output signal rise time 27
tF Differential output signal fall time 48
VSYM Driver symmetry (VO(CANH) + VO(CANL))/VCC RTERM = 60 Ω, CL = open, CSPLIT = 4.7nF, TXD = Dominant or receissive or toggling at 250khz, 1Mhz See Figure 9-3  0.9 1.1 V/V
tTXD_DTO Dominant time out RL = 60 Ω and CL = open, See GUID-20200710-SS0I-JPX8-LTFT-RNRQCRR6XDXR 1.2 3.8 ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH Propagation delay time, bus dominant to recessive transition to RXD high output (dominant to recessive) CL(RXD) = 15 pF, See Figure 9-5 90 115 ns
tpDL Propogation delay time, bus recessive to dominant transition to RXD low output (recessive to dominant) 80 105 ns
tR Output signal rise time(RXD) 1 ns
tF Output signal fall time(RXD) 1 ns
FD TIMING PARAMETERS
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns, See Figure 9-6 435 530 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns, See Figure 9-6 155 210 ns
tBIT(RXD) Bit time on RXD bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns, See Figure 9-6 400 550 ns
Bit time on RXD bus output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns, See Figure 9-6 120 220 ns
∆tREC Receiver timing symmetry with tBIT(TXD) = 500 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS), See Figure 9-6 -65 40 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS), See Figure 9-6 -45 15 ns
GPIO Channel
tPLH, tPHL Propagation delay time 11 25 ns
PWD Pulse Width distortion, |tPLH- tPHL| 3.5 10 ns
tr Output signal rise time 2.2 5 ns
tf Output signal fall time 2.2 5 ns