SLLSFJ1D February   2022  – March 2023 TIOL112 , TIOL1123 , TIOL1125

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL112)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

9.2.3 Application Curves

GUID-3F94375C-0A06-40AD-BAD9-44E3226669A3-low.gif
Figure 9-4 CQ in Current Fault Auto Recovery, Low Side Mode
GUID-20221117-SS0I-TWDC-SX34-WT9JSDHCKB5P-low.png
L+ = 36 V L = 1.5 H RL = 360 Ω RSET = 10 kΩ TA = 25 °C
Figure 9-6 CQ Driving Inductive Load, Low Side Mode (NPN mode)
GUID-20220128-SS0I-WDCS-VXMG-B3KMC4DHJHFL-low.png
NFAULT is indicated for the duration of charging and discharging of the capacitor but driver is not disabled when ILIM_ADJ is floating
L+ = 24 V CL = 20 µF RL = 100 Ω RSET = 1 MΩ (ILIM_ADJ Floating) TA = 25 °C
Figure 9-8 CQ Driving Capacitive Load, Push-Pull Mode
GUID-C6184FD3-A462-4045-A913-F54F136F937F-low.gif
Figure 9-5 CQ in Current Fault Auto Recovery, High Side Mode
GUID-20221117-SS0I-SDRD-CDL5-GQRNVZCG1FMZ-low.png
L+ = 36 V L=1.5 H RL = 360 Ω RSET = 10 kΩ TA = 25 °C
Figure 9-7 CQ Driving Inductive Load, High Side Mode (PNP mode)