SLLSFJ1D February   2022  – March 2023 TIOL112 , TIOL1123 , TIOL1125

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL112)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TIOL112
DRC (VSON), 10-Pin
(Top View)
Figure 5-2 TIOL1123, TIOL1125
DRC (VSON), 10-Pin
(Top View)
Table 5-1 Pin Functions (VSON Package)
PIN NOPIN NAMETYPE DESCRIPTION
TIOL112TIOL1123 TIOL1125
1VCC_INVCC_OUTPVCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123, TIOL1125): 3.3-V or 5-V linear regulator output
2NFAULTNFAULTO Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an undervoltage supply or an overtemperature condition.
3RXRXOReceive data output to the local microcontroller
4TXTXITransmit data input from the local microcontroller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up.
5ENENIDriver enable input signal from the local microcontroller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down.
6ILIM_ADJILIM_ADJIInput for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
7L-L-GNDIO-Link ground potential
8CQCQI/OIO-Link data signal (bidirectional)
9L+L+PIO-Link supply voltage (24 V nominal)
10WAKEWAKEOWake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up resistor to VCC_IN/OUT.
Thermal PadThermal Pad—Connect to L- for optimal thermal and electrical performance
Figure 5-3 TIOL1123L
YAH (DSBGA), 12-Pin
(Top View)
Figure 5-4 TIOL112
YAH (DSBGA), 12-Pin
(Top View)
Table 5-2 Pin Functions (DSBGA)
PIN NOPIN NAMETYPEDESCRIPTION
TIOL112TIOL1123L
B3VCC_INVCC_OUTPVCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123): 3.3-V or 5-V linear regulator output
C3NFAULTNFAULTO Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an undervoltage supply or an overtemperature condition.
D1RXRXOReceive data output to the local controller
D2TXTXITransmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up.
D3ENENIDriver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down.
B1ILIM_ADJILIM_ADJOInput for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
A1,

B2

L-L-

GND

IO-Link ground potential
A2CQCQI/OIO-Link data signal (bidirectional)
A3L+L+PIO-Link supply voltage (24 V nominal)
C1NCVSELITIOL112 (NC): Leave floating. Do not connect. TIOL1123 (VSEL): Connect to GND for 5V LDO output. Please leave this pin floating for 3.3V LDO output. VSEL has an internal pull-up of 1 MΩ
C2WAKEWAKE

O

Wake-up indicator to the local controller. Open-drain output, connect this pin via pull-up resistor to VCC_IN/OUT.