SLLSFL1A April   2022  – May 2024 TUSB1104

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.2 x2 Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1104 I2C Address Options
      3. 7.5.3 TUSB1104 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 Device Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB SSTX1/2 Receiver Configuration
        2. 8.2.2.2 USB CRX1/2 Receiver Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Full Adaptive Equalization
          3. 8.2.2.2.3 Fast Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Linear EQ Configuration

Each of the TUSB1104 receiver lanes have individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through pin-straps. Table 7-2 and Table 7-3 details the gain value for each available combination when TUSB1104 is in pin-strap mode. These same options are also available in I2C mode by updating registers CEQ1_SEL, CEQ2_SEL, SSEQ2_SEL, and SSEQ1_SEL.

Table 7-2 USB Connector Facing Port Receiver (CRX1 and CRX2 pins) Equalization Control
Register(s): CEQ1_SEL or CEQ2_SEL
Equalization Setting #
CEQ1 PIN LevelCEQ0 PIN LevelEQ Gain at 5 GHz minus Gain at 100 MHz
(dB)
000-0.4
10R1.9
20F3.5
3015.0
4R06.1
5RR7.2
6RF8.0
7R18.8
8F09.6
9FR10.2
10FF10.7
11F111.2
121011.6
131R12.0
141F12.4
151112.7
Table 7-3 USB Host Facing Port Receiver (SSTX1 and SSTX2 pins) Equalization Control
Register(s): SSEQ1_SEL or SSEQ2_SEL
Equalization Setting #
SSEQ1 PIN LEVELSSEQ0 PIN LEVELEQ Gain at 5 GHz minus Gain at 100 MHz
(dB)
0000.6
10R2.8
20F4.5
3016.0
4R07.0
5RR8.0
6RF9.0
7R110.0
8F010.6
9FR11.2
10FF11.7
11F112.2
121012.5
131R13.0
141F13.3
151113.6