SLLSFL2A April 2022 – May 2024 TUSB1142
PRODUCTION DATA
Each of the TUSB1142 receiver lanes have individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through pin-straps. Table 7-2 and Table 7-3 details the gain value for each available combination when TUSB1142 is in pin-strap mode. These same options are also available in I2C mode by updating registers CEQ1_SEL, CEQ2_SEL, and SSEQ1_SEL.
| Register(s): CEQ1_SEL or CEQ2_SEL Equalization Setting # | CEQ1 PIN Level | CEQ0 PIN Level | EQ Gain at 5 GHz minus Gain at 100 MHz (dB) |
|---|---|---|---|
| 0 | 0 | 0 | -0.4 |
| 1 | 0 | R | 1.9 |
| 2 | 0 | F | 3.5 |
| 3 | 0 | 1 | 5.0 |
| 4 | R | 0 | 6.1 |
| 5 | R | R | 7.2 |
| 6 | R | F | 8.0 |
| 7 | R | 1 | 8.8 |
| 8 | F | 0 | 9.6 |
| 9 | F | R | 10.2 |
| 10 | F | F | 10.7 |
| 11 | F | 1 | 11.2 |
| 12 | 1 | 0 | 11.6 |
| 13 | 1 | R | 12.0 |
| 14 | 1 | F | 12.4 |
| 15 | 1 | 1 | 12.7 |
| Register(s): SSEQ1_SEL Equalization Setting # | SSEQ1 PIN LEVEL | SSEQ0 PIN LEVEL | EQ Gain at 5 GHz minus Gain at 100 MHz (dB) |
|---|---|---|---|
| 0 | 0 | 0 | 0.6 |
| 1 | 0 | R | 2.8 |
| 2 | 0 | F | 4.5 |
| 3 | 0 | 1 | 6.0 |
| 4 | R | 0 | 7.0 |
| 5 | R | R | 8.0 |
| 6 | R | F | 9.0 |
| 7 | R | 1 | 10.0 |
| 8 | F | 0 | 10.6 |
| 9 | F | R | 11.2 |
| 10 | F | F | 11.7 |
| 11 | F | 1 | 12.2 |
| 12 | 1 | 0 | 12.5 |
| 13 | 1 | R | 13.0 |
| 14 | 1 | F | 13.3 |
| 15 | 1 | 1 | 13.6 |