SLLSFO9A May   2024  – September 2024 TUSB564-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 USB 3.2
      2. 7.3.2 DisplayPort
      3. 7.3.3 4-Level Inputs
      4. 7.3.4 Receiver Linear Equalization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Configuration in GPIO Mode
      2. 7.4.2 Device Configuration In I2C Mode
      3. 7.4.3 DisplayPort Mode
      4. 7.4.4 Linear EQ Configuration
      5. 7.4.5 USB3 Modes
      6. 7.4.6 Operation Timing – Power Up
    5. 7.5 Programming
      1. 7.5.1 TUSB564-Q1 I2C Target Behavior
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ESD Protection
        2. 8.2.2.2 Support for DisplayPort UFP_D Pin Assignment E
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 General Register (address = 0x0A) [reset = 00000001]
    2. 9.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
    3. 9.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
    4. 9.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
    5. 9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
    6. 9.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
    7. 9.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
    8. 9.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]

Figure 9-5 DisplayPort Control/Status Registers (0x13)
76543210
AUX_SNOOP_DISABLEReservedAUX_SBU_OVRDP3_DISABLEDP2_DISABLEDP1_DISABLEDP0_DISABLE
R/WRR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-6 DisplayPort Control/Status Registers (0x13)
BitFieldTypeResetDescription
7AUX_SNOOP_DISABLER/W00: AUX snoop enabled. (Default)
1: AUX snoop disabled.
6ReservedR0Reserved
5:4AUX_SBU_OVRR/W00This field overrides the AUXp or AUXn to SBU1 or SBU2 connect and disconnect based on CTL1 and FLIP. Changing this field to 2’b01 or 2'b10 allows traffic to pass through AUX to SBU regardless of the state of CTLSEL1 and FLIPSEL register
00: AUX to SBU connect/disconnect determined by CTLSEL1 and FLIPSEL (Default)
01: AUXn -> SBU1 and AUXp -> SBU2 connection always enabled.
10: AUXn -> SBU2 and AUXp -> SBU1 connection always enabled.
11: AUX to SBU open.
3DP3_DISABLER/W0When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 3. When AUX_SNOOP_DISABLE = 1’b0, changes to this field have no effect on lane 3 functionality.
0: DP Lane 3 Enabled (default)
1: DP Lane 3 Disabled.
2DP2_DISABLER/W0When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 2. When AUX_SNOOP_DISABLE = 1’b0, changes to this field have no effect on lane 2 functionality.
0: DP Lane 2 Enabled (default)
1: DP Lane 2 Disabled.
1DP1_DISABLER/W0When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 1. When AUX_SNOOP_DISABLE = 1’b0, changes to this field have no effect on lane 1 functionality.
0: DP Lane 1 Enabled (default)
1: DP Lane 1 Disabled.
0DP0_DISABLER/W0DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 1’b0, changes to this field have no effect on lane 0 functionality.
0: DP Lane 0 Enabled (default)
1: DP Lane 0 Disabled.