SLLSFP1A May 2024 – September 2024 TUSB521-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
I2C (SDA and SCL) | ||||||
fSCL | I2C clock frequency | 1 | MHz | |||
tBUF | Bus free time between START and STOP conditions | 0.5 | µs | |||
tHDSTA | Hold time after repeated START condition. After this period, the first clock pulse is generated | 0.26 | µs | |||
tLOW | Low period of the I2C clock | 0.5 | µs | |||
tHIGH | High period of the I2C clock | 0.26 | µs | |||
tSUSTA | Setup time for a repeated START condition | 0.26 | µs | |||
tHDDAT | Data hold time | 0.004 | µs | |||
tSUDAT | Data setup time | 50 | ns | |||
tR | Rise time of both SDA and SCL signals | 120 | ns | |||
tF | Device output fall time for SDA | 30pF load | 0.7 | 5 | ns | |
tSUSTO | Setup time for STOP condition | 0.26 | µs | |||
Cb | Capacitive load for each bus line | 100 | pF |