SLLSG10 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

6.5 Programming

For further programmability, the TDP142-Q1 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA pins are used for I2C clock and I2C data, respectively.

Table 6-4 TDP142-Q1 I2C Target Address
DPEQ0/A1
PIN LEVEL		A0
PIN LEVEL		BIT 7 (MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 (W/R)
0010001000/1
0R10001010/1
0F10001100/1
0110001110/1
R001000000/1
RR01000010/1
RF01000100/1
R101000110/1
F000100000/1
FR00100010/1
FF00100100/1
F100100110/1
1000011000/1
1R00011010/1
1F00011100/1
1100011110/1

Use the following procedure to write to TDP142-Q1 I2C registers:

  1. The controller initiates a write operation by generating a start condition (S), followed by the TDP142-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TDP142-Q1 acknowledges the address cycle.
  3. The controller presents the sub-address (I2C register within TDP142-Q1) to be written, consisting of one byte of data, MSB-first.
  4. The TDP142-Q1 acknowledges the sub-address cycle.
  5. The controller presents the first byte of data to be written to the I2C register.
  6. The TDP142-Q1 acknowledges the byte transfer.
  7. The controller can continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TDP142-Q1.
  8. The controller terminates the write operation by generating a stop condition (P).

Use the following procedure to read the TDP142-Q1 I2C registers:

  1. The controller initiates a read operation by generating a start condition (S), followed by the TDP142-Q1 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  2. The TDP142-Q1 acknowledges the address cycle.
  3. The TDP142-Q1 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TDP142-Q1 starts at the sub-address specified in the write.
  4. The TDP142-Q1 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.
  5. If an ACK is received, the TDP142-Q1 transmits the next byte of data.
  6. The controller terminates the read operation by generating a stop condition (P).

Use the following procedure for setting a starting sub-address for I2C reads:

  1. The controller initiates a write operation by generating a start condition (S), followed by the TDP142-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TDP142-Q1 acknowledges the address cycle.
  3. The controller presents the sub-address (I2C register within TDP142-Q1) to be written, consisting of one byte of data, MSB-first.
  4. The TDP142-Q1 acknowledges the sub-address cycle.
  5. The controller terminates the write operation by generating a stop condition (P).

Note:

If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C controller terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.

Table 6-5 Register Legend
ACCESS TAGNAMEMEANING
RReadThe field can be read by software
WWriteThe field can be written by software
SSetThe field can be set by a write of one. Writes of zeros to the field have no effect.
CClearThe field can be cleared by a write of one. Write of zero to the field have no effect.
UUpdateHardware may autonomously update this field.
NANo AccessNot accessible or not applicable