SLLSG10 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

8.4.1 Layout Guidelines

  1. Route the INDP[3:0]P/N and OUTDP[3:0]P/N pairs swith controlled 100Ω differential impedance (±10%).
  2. Keep away from other high speed signals.
  3. Keep intra-pair routing within 5 mils.
  4. Keep inter-pair skew within 2 UI according to the DisaplyPort Design Guide
  5. Make sure length matching is near the location of mismatch.
  6. Separate each pair by at least 3 times the signal trace width.
  7. Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of left and right bends are as equal as possible and that the angle of the bend is ≥ 135 degrees. This setup minimizes any length mismatch caused by the bends and therefore minimize the impact bends have on EMI.
  8. Route all differential pairs on the same of layer.
  9. Keep the number of VIAS to a minimum. TI recommends to keep the VIAS count to 2 or less.
  10. Refer to Figure 8-7, the layout might face signal crossing on OUTDP2 and OUTDP3 due to mismatched order between the output pins of the device and the connector. One solution is to do a polarity swap on the input of the device when GPU is a BGA package to help minimize the number of VIAS being used.
  11. Keep traces on layers adjacent to ground plane.
  12. Do NOT route differential pairs over any plane split.
  13. Adding test points can cause impedance discontinuity, and therefore, negatively impact signal performance. If test points are used, place the test points in series and symmetrically. Do not place test points in a manner that causes a stub on the differential pair.