This user's guide details the evaluation module (EVM) operation of the ISO721 and ISO721M digital isolators. The same EVM board is used for each device. Configuration requirements are presented as well as user optional I/O loads. This document is intended to aid designers with isolator parameter performance evaluation within a particular system.
The ISO721 and ISO721M digital isolators have a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, and then differentiated by the SiO2 isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 μs, the input is assumed to be unpowered or not functional, and the fail-safe circuit drives the output to a logic-high state.
Note that although these devices provide galvanic isolation of up to 4000 V, this EVM cannot be used for isolation voltage testing. It is designed for the examination of device operating parameters only and will be damaged if high voltage (> 5.5 V) is applied anywhere in the circuit.
The EVM is configured for the pinout displayed in Figure 3-1. The additional I/Os on the EVM are provided for future development.
The ISO721 has TTL input thresholds and a input noise filter that prevents transient pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M has a CMOS VCC/2 input threshold and does not have the noise filter and the additional propagation delay. These features of the ISO721M also provide for a 0-Mbps to 150-Mbps signaling rate rather than the ISO721’s 0-Mbps to 100-Mbps signaling rate.
This multifunctional EVM is designed with signal paths shown in Figure 4-1 for the analysis of the ISO721 and ISO721M, as well as future isolator configurations.
Connection | Label | Description |
---|---|---|
J1 | SMA connector (unused) | |
J2 | SMA connector to the output pin 6 | |
J3 | SMA connector to the input pin 2 | |
J4 | SMA connector (unused) | |
P1 | VCC1 | Input power supply banana jack |
P2 | VCC2 | Output power supply banana jack |
P3 | GND1 | Input power ground connection banana jack |
P4 | GND2 | Output power ground connection banana jack |
JMP1 | 3-pin jumper (unused) | |
JMP2 | 3-pin jumper (unused) | |
JMP3 | 3-pin jumper – VCC1, input, GND1 | |
JMP4 | 3-pin jumper (unused) |
The ISO721EVM configuration has an SMA connector J3 set up as the input to pin 2, the IN pin of the ISO721 in Figure 3-1 and Figure 4-1. A 0-Ω input series resistor, R8, is located next to the J3 input connector, and a 50-Ω R5 from the input to ground is located on the bottom of the board.
The output channel configuration of the ISO721EVM has the OUT pin (pin 6) of Figure 3-1 and Figure 4-1 connected to SMA connector J2 through a 0- Ω series resistor R4.
The pads for R3, C12, and C13 are available on the bottom of the EVM for varied loading conditions if desired by a user.