SLLU149E June   2011  – February 2016 TUSB7320 , TUSB7340

 

  1.   TUSB73x0 Board Design and Layout Guidelines
    1.     Trademarks
    2.     Related Documentation
  2. 1 Typical System Implementation
    1. 1.1 Overview
  3. 2 Power
    1. 2.1 Overview
    2. 2.2 Digital Supplies
    3. 2.3 Analog Supplies
    4. 2.4 Ground Terminal
    5. 2.5 Capacitor Selection Recommendations
    6. 2.6 USB VBUS
  4. 3 Device Reset
    1. 3.1 Overview
  5. 4 General High Speed Layout Guidelines
    1. 4.1 Printed Circuit Board Stackup (FR-4 Example)
    2. 4.2 Return Current and Plane References
    3. 4.3 Split Planes – What to Avoid
    4. 4.4 Avoiding Crosstalk
  6. 5 USB Connection
    1. 5.1 Overview
    2. 5.2 Internal Chip Trace Length Mismatch
    3. 5.3 High-Speed Differential Routing
    4. 5.4 SuperSpeed Differential Routing
  7. 6 Package and Breakout
    1. 6.1 Package Drawing
    2. 6.2 Routing Between Pads
    3. 6.3 Pads
    4. 6.4 Land Pattern Recommendation
    5. 6.5 Solder Stencil
  8. 7 PCI Express Connection
    1. 7.1 Internal Chip Trace Length Mismatch
    2. 7.2 Transmit and Receive Links
    3. 7.3 PCI-Express Reference Clock Input
    4. 7.4 PCI Express Reset
    5. 7.5 PCI Express WAKE/CLKREQ
      1. 7.5.1 Leakage Current on Pins WAKE# and CLKREQ#
      2. 7.5.2 Recommendations
  9. 8 Wake from S3
    1. 8.1 Overview
  10. 9 Device Input Clock
    1. 9.1 Overview
  11. 10JTAG Interface
    1. 10.1 Overview
  12. 11Differential Pair ESD Protection
    1. 11.1 Overview
  13. 12SuperSpeed Redriver
    1. 12.1 Overview
  14. 13SMI Pin Implementation
    1. 13.1 Overview
  15. 14Schematics
    1. 14.1 Overview
    2. 14.2 TUSB7320 DEMO EVM REVB Schematics
    3. 14.3 TUSB7340 DEMO EVM REVB Schematics
  16.   Revision History

5.3 High-Speed Differential Routing

The high-speed differential pair (USB_DM and USB_DP) is connected to a type A USB connecter. The differential pair traces should be routed with 90 Ω ±15% differential impedance. The high-speed signal pair should be trace length matched. Max trace length mismatch between high speed USB signal pairs should be no greater than 150 mils. Keep total trace length to a minimum, if routing longer than eight inches contact TI to address signal integrity concerns.

Route differential traces first. Route the differential pairs on the top or bottom layers with the minimum amount of vias possible. No termination or coupling caps are required. If a common mode choke is required then place the choke as close as possible to the USB connector signal pins. Likewise ESD clamps should also be placed as close as possible to the USB connector signal pins (closer than the choke).

For more detailed information, you may also see the USB 2.0 Board Design and Layout Guidelines (SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0 differential pair (DP/DM).