SLLU322A September   2020  – October 2022 ISO1640

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Overview
  5. 3Pin Configurations of Isolated I2C Transceivers
  6. 4EVM Setup and Operation
  7. 5Bill of Materials
  8. 6EVM Schematic and PCB

EVM Schematic and PCB

The ISO1640 isolated I2C EVM comes with an ISO1640D installed in place of U1. This EVM can also be configured for use with an ISO1641D, ISO1640DW, or ISO1641DW.

Each signal line (SDAx, SCLx) is configured with a 4.75-kΩ pull-up resistor (R1 to R4) to the corresponding power supply (Vccx). These resistors may be replaced with 0805 resistors of other values per the application requirements; for insight on calculating approprate pull-up resistor values for I2C buses, please refer to SLVA689, I2C Bus Pullup Resistor Calculation.

Note: ISO164x devices are designed to sink different amounts of current on Side 1 and Side 2, so be careful to choose resistors that keep IOL1 and IOL2 within the recommended operating range if replacing resistors R1 to R4.

Signal pins my be tied directly to ground using the ground jumpers (P3 and P5 on side 1; P4 and P6 on side 2) to simulate a device pulling the I2C line low. While not being actively driven low, the lines will be pulled up through the included pull-up resistors. Signal lines should not be tied directly to a supply voltage without a pull-up resistor to limit input current. These jumpers also provide input /output signal access, including for oscilloscope probes, to each pin.

Note: Ensure that SDAx and SCLx signal lines are not tied directly to Vccx. A current-limiting pull-up resistor is required, and populated by default, to limit current in the cases where the device pins drive a low-voltage.

A schematic diagram for this EVM is shown in Figure 6-1 below, and Figure 6-2 and Figure 6-3 show the printed circuit board (PCB) layout.


GUID-20200924-CA0I-NNVX-1K6G-SMZM9BMNXTDS-low.png
Figure 6-1 ISO1640DEVM Schematic
GUID-20200924-CA0I-KP4M-SKGH-JG3TBXP1HGXC-low.png Figure 6-2 ISO1640DEVM Top PCB Layout
GUID-20200924-CA0I-52DR-2F5R-DBT7WRWRVZLM-low.png Figure 6-3 ISO1640DEVM Bottom PCB Layout